ADP1763 datasheet(13/62 Pages) AD

13 / 62 page

Data Sheet

LT3074

analog.com

Rev 0.

13 of 62

ALERT

Open-Drain Digital Output. Connect the SMBALERT signal to this pin. A pull-up

resistor to the highest supply rail is required in the application.

SCL

Serial Bus Clock Input. Open-Drain Output. A pull-up resistor to the highest supply rail

is required in the application.

SDA

Serial Bus Data Input and Output. Open-Drain Output. A pull-up resistor to the highest

supply rail is required in the application.

Power Good. PG is an open-drain flag that indicates output voltage regulation. PG

pulls low if PGFB is below 300mV on the PGFB rising edge. If power good functionality

is not needed, float the PG pin. See the Applications Information section for more

information.

PGFB

Power Good Feedback. The PG pin pulls high if the PGFB pin increases beyond 300mV

on its rising edge, with 8mV hysteresis on its falling edge. Connecting an external

resistor divider between OUT, PGFB, and AGND sets the programmable power good

threshold with the following transfer function: 0.3V x (1 + RPG2/RPG1), where RPG1 is the

resistor tied from PGFB to AGND and RPG2 is the resistor tied from OUT to PGFB. Tie

PGFB to BIASAF if power good functionality is not required.

8, 9,

Exposed

Pad 24

OUT

Output. Pins 8, 9, and exposed pad 24 of the LQFN package are the electrical

connection to OUT. These pins supply power to the load. Tie all OUT pins together for

proper performance and solder pin 24 to the PCB for better thermal performance. A

minimum output capacitance of 10µF is required for stability. Analog Devices

recommends low ESR, X5R, or X7R dielectric ceramic capacitors for best performance.

Large load transient applications require larger output capacitors to limit peak voltage

transients.

SENSE

Kelvin Sense for OUT. The SENSE pin is the inverting input to the error amplifier.

Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of

the regulator. In critical applications, the resistance of PCB traces between the

regulator and the load causes small voltage drops, creating a load regulation error at

the point of load. Connecting the SENSE pin at the load instead of directly to OUT

eliminates this voltage error.

AGND

Analog Ground. To ensure proper electrical and thermal performance, tie all ground

pins of the package to PCB ground.

SETCAP

Reference Filter. This pin must not be externally loaded. Bypassing the SETCAP pin to

AGND with a 4.7µF capacitor decreases output voltage noise and provides a soft-start

function to the reference. Analog Devices recommends the use of a high quality, low

leakage capacitor.

SETRES

Reference. This pin sources the 100µA precision current. Placing a resistor from this

pin to the AGND pin of the LT3074 sets the output regulation voltage.

IMON

Output Current Monitor. The IMON pin is a voltage output pin that sources a voltage

proportional to the output current with a ratio of 3A/V. For best performance, minimize

the external loading on this pin and do not drive the pin externally.

ASEL

Serial Bus Address Select. This pin allows programming the 4LSBs out of the 7-bit

address space. The 3MSBs are hardwired to 110b. Connect a ±1% resistor divider

between BIASAF, ASEL, and AGND to select the serial bus interface address. Optionally,

ADP1763 数据表(PDF) 13 Page - Analog Devices

ADP1763 数据表(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载