7 Register Maps

7.1 CDCDB2000 Registers

Table 7-1 lists the CDCDB2000 registers. All register locations not listed in Table 7-1 should be considered as

reserved locations and the register contents should not be modified.

Table 7-1. CDCDB2000 Registers

Address

Acronym

Register Name

Section

0h

OECR1

Output Enable Control 1

Go

1h

OECR2

Output Enable Control 2

Go

2h

OECR3

Output Enable Control 3

Go

3h

OERDBK

Output Enable Read Back

Go

4h

SBRDBK

SBEN Read Back

Go

5h

VDRREVID

Vendor/Revision Identification

Go

6h

DEVID

Device Identification

Go

7h

BTRDCNT

Byte Read Count Control

Go

8h

SBIMSK1

Side-Band Interface Override Control 1

Go

9h

SBIMSK2

Side-Band Interface Override Control 2

Go

Ah

SBIMSK3

Side-Band Interface Override Control 3

Go

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for

access types in this section.

Table 7-2. CDCDB2000 Access Type Codes

Access Type

Code

Description

Read Type

R

R

Read

Write Type

W

W

Write

Reset or Default Value

-n

Value after reset or the default

value

7.1.1 OECR1 Register (Address = 0h) [reset = 78h]

OECR1 is shown in Table 7-3.

Return to the Summary Table.

The OECR1 register contains bits that enable or disable individual output clock channels [19:16]

Table 7-3. OECR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R

0h

Reserved

6

Output Enable, CK19

R/W

1h

This bit controls the output enable signal for output channel CK19_P/

CK19_N.

0h = Output Disabled

1h = Output Enabled

5

Output Enable, CK18

R/W

1h

This bit controls the output enable signal for output channel CK18_P/

CK18_N.

0h = Output Disabled

1h = Output Enabled

CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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