8.2.2 Detailed Design Procedure

The following items must be determined before starting design of a CDCDB2000 socket:

• Output Enable Control Method

8.2.2.1 Output Enable Control Method

The device provides an option to either use SMBus programmed registers (software) to control the outputs or by

using the hardware OE# pins. In case of using software to control the outputs, the hardware OE# pins can be left

floating as each of these pins have a pulldown to ground. Refer to the Section 7 section for more information on

programming the register.

When the user wants to control the outputs with the hardware OE# pins, they can do so for example by

connecting these pins to a GPIO controller and follow the Section 4 section to set the outputs to HIGH/LOW.

The bits OUT_EN_CLK7 to OUT_EN_CLK0 used to control the outputs are shown in registers OECR1 field

descriptions. These register bits are set to 1 by default to ensure that the outputs are "software enabled" and

their state is therefore set by hardware OE# pins.

8.2.2.2 SMBus Address

An SMBus address should be selected from the listed potential addresses in Table 8-1. The appropriate pullup or

pulldown resistor should be placed on the SADRx pins as indicated in the table. Ensure the SMBus address is

not already in use to avoid conflict.

Table 8-1. SMBus Address Assignment

SADR1

SADR0

SMBus ADDRESS

L

L

0xD8

L

M

0xDA

L

H

0xDE

M

L

0xC2

M

M

0xC4

M

H

0xC6

H

L

0xCA

H

M

0xCC

H

H

0xCE

8.2.3 Application Curve

The graph listed in Table 8-2 is used as both an application curve and a typical characteristics plot (see the

Section 5.7 section).

Table 8-2. Table of Graphs

TITLE

FIGURE

CDCDB2000 Clock Out (CK0:19) Phase Noise

Figure 5-1

8.3 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

the jitter and phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the very low impedance path for high-frequency noise and guards the power supply system

against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by

the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they

must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI

recommends to insert a ferrite bead between the board power supply and the chip power supply that isolates the

high-frequency switching noises generated by the clock buffer. These beads prevent the switching noise from

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CDCDB2000

SNAS787B – NOVEMBER 2019 – REVISED OCTOBER 2024

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