TLE2072, TLE2072A, TLE2072Y

EXCALIBUR LOW-NOISE HIGH-SPEED

JFET-INPUT DUAL OPERATIONAL AMPLIFIERS

SLOS124A – JUNE 1993 – REVISED AUGUST 1994

5–35

POST OFFICE BOX 655303

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using

PSpice

™ Parts™ model generation software. The Boyle

macromodel (see Note 4) and subcircuit in Figure 58 were generated using the TLE2072 typical electrical and

can be generated to a tolerance of 20% (in most cases):

NOTE 4: G.R. Boyle, B.M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”,

IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

OUT

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

.SUBCKT TLE2072 1 2 3 4 5

C1

11

12

2.2E–12

C2

6

7

10.00E–12

DC

5

53

DX

DE

54

5

DX

DLP

90

91

DX

DLN

92

90

DX

DP

4

3

DX

EGND

99

0

POLY (2) (3,0) (4,0) 0 .5 .5

FB

7

99

POLY (5) VB VC VE VLP

+ VLN 0 5.607E6 –6E6 6E6 6E6 –6E6

GA

6

0

11 12 333.0E–6

GCM

0

6

10 99 7.43E–9

ISS

3

10

DC 400.0E–6

HLIM

90

0

VLIM 1K

J1

11

2

10 JX

J2

12

1

10 JX

RD1

4

11

3.003E3

RD2

4

12

3.003E3

R01

8

580

R02

7

99

80

RP

3

4

27.30E3

RSS

10

99

500.0E3

VB

9

0

DC 0

VC

3

53

DC 2.20

VE

54

4

DC 2.20

VLIM

7

8

DC 0

VLP

91

0

DC 45

VLN

0

92

DC 45

.MODEL DX D (IS=800.0E–18)

.MODEL JX PJF (IS=15.00E–12 BETA=554.5E–6

+ VTO=–.6)

.ENDS

VCC +

RP

IN –

2

IN+

1

VCC –

RD1

11

J1

J2

10

RSS

ISS

3

12

RD2

VE

54

DE

DP

VC

DC

C1

53

R2

6

9

EGND

VB

FB

C2

GCM

GA

VLIM

8

5

RO1

RO2

HLIM

90

DIP

91

DIN

92

VIN

VIP

99

7

4

R2

6

9

100.0E3

Figure 58. Boyle Macromodel and Subcircuit

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