SWIFT® Technology

Silicon Wafer Integrated Fan-out Technology (SWIFT) is designed

to provide increased I/O and circuit density in a reduced footprint

and profile for single and multi-die applications. SWIFT technology

enables creation of advanced 3D structures, addressing the need

for increased IC integration in emerging mobile and networking

applications.

The distinctive characteristics of SWIFT technology are due, in part, to

the fine feature capabilities associated with this innovative wafer level

packaging technique. This allows more aggressive design rules to be

applied compared to traditional WLFO and laminate-based assemblies.

SWIFT Structures and Attributes

The figure below shows cross-section illustrations of a single die SWIFT

and dual-die 3D/Package-on-Package (PoP) SWIFT structures. Although

the package appears to be of a typical fine-pitch flip chip construction, it

incorporates some unique features not

associated with conventional IC packages.

Enabling Technologies for

SWIFT Packaging

Key assembly technologies enable the

creation of these distinctive SWIFT

packaging features and attributes.

Through the use of stepper photo imaging

equipment, 2/2 μm line/space features can

be achieved, enabling very high density

die-to-die connections required for SoC

partitioning and networking applications

where 2.5D TSV would typically be used.

Fine-pitch die micro bumps provide a

high-density interconnect for advanced

products, such as application processors

and baseband devices. In addition, tall

Cu pillars enable a high-density vertical

interface for mounting advanced memory

devices on the top of the SWIFT structure.

SWIFT® PACKAGING

CONSIDERATIONS

Amkor’s state-of-the-art High-Density

Fan-Out (HDFO) structure called

Silicon Wafer Integrated Fan-out

Technology (SWIFT) packaging,

bridges the gap between TSV and

laminate substrates.

FEATURES

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Polymer dielectrics

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Multi-die and large die capability

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Large body package capability

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Interconnect density down to

2/2 μm

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Cu pillar die interconnect down to

30 μm pitch

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Meets JEDEC MSL2a and MSL3 CLR

and BLR requirements

SWIFT® on Substrate

Fan-in PoP SWIFT®

Plated Cu RDL L/S

down to 2 µm

Multilayer

Redistribution

Multilayer RDL

Cross Section

Tall Cu Pillar for

PoP Applications

TECHNOLOGY SOLUTIONS