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SWIFT® Technology

SWIFT Packaging Process Flow

SWIFT product attributes are realized by applying a

unique process flow that incorporates both flip chip

assembly and wafer level processing techniques, as

shown below.

Reliability Data

Component Level

Board Level

MSL2aA,

MSLA3 Precon

Unbiased

HAST 192

hrs

TCB 1500

cycles

HTS 1000

hrs

Drop

Temp

Cycle

Pass

Pass

Pass

Pass

Pass

Pass

SWIFT Packaging Technology Process Flow

Advanced Wafer Product Positioning

Tall Cu Pillars

250 μm pitch

40 μm pitch

< 0.30

mm

Total

Height

Carrier

Carrier

RDL & Copper Pillar

Bump (3D Only)

Chip Attach & UF

Wafer Mold

Carrier Remove

RDL for Memory

Interface

Top Side Routing

for Memory

Interface

f

Multi-die, SoC partition, 3D PoP-compatible

f

≤2 μm L/S routing by foundry BEOL interposer

f

High performance (CPU/GPU), mobile AP, BB

f

Single die

f

RDL ≥10 μm by Amkor bump line

f

RF, WLAN, Power, etc.

Products: RF and analog to advanced processors

Performance

WLCSP

Fan-Out

SWIFT®

f

Multi-die, SoC partition, HBM, 3D PoP-compatible

f

RDL 2~10 μm by Amkor bump line; mobile AP/BB

f

Single or multi-die integration

f

RDL 6~12 μm by Amkor bump line; RFIC & PMIC