VDIP2 Vinculum VNC1L Prototyping Module

Datasheet Version 0.91

© Future Technology Devices Intl Ltd. 2006-2007

Page 

2.�� Para����e�� �I�O Inter�a�e �igna�� �es�riptions and Timing �iagrams

2.��Para����e���I�OInter�a�e�igna���es�riptionsandTiming�iagrams

Table 5 - Data and Control Bus Signal Mode Options - Parallel FIFO Interface

Pin No.

Name

Type

Description

14

D0

I/O

FIFO Data Bus Bit 0

16

D1

I/O

FIFO Data Bus Bit 1

17

D2

I/O

FIFO Data Bus Bit 2

18

D3

I/O

FIFO Data Bus Bit 3

19

D4

I/O

FIFO Data Bus Bit 4

20

D5

I/O

FIFO Data Bus Bit 5

21

D6

I/O

FIFO Data Bus Bit 6

22

D7

I/O

FIFO Data Bus Bit 7

23

RXF#

OUTPUT

When high, do not read data from the FIFO. When low, there is data available in the FIFO which can

bereadbystrobingRD#low,thenhighagain.

24

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing

WR high, then low.

25

RD#

INPUT

EnablesthecurrentFIFOdatabyteonD0...D7whenlow.FetchedthenextFIFOdatabyte(ifavail-

able)fromthereceiveFIFObufferwhenRD#goesfromhightolow.

27

WR

INPUT

Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low.

Figure 3 - FIFO Read Cycle

RXF#

RD#

D[7...0]

T3

T1

T5

T6

T2

T4

Valid Data

Table 6 - FIFO Read Cycle Timings

Time

Description

Min

Max

Unit

T1

RD Active Pulse Width

50

-

ns

T2

RD to RD Pre-Charge Time

50 + T6

-

ns

T3

RD Active to Valid Data*

20

50

ns

T4

Valid Data Hold Time from RD Inactive* 0

-

ns

T5

RDInactivetoRXF#

0

25

ns

T6

RXF Inactive After RD Cycle

80

-

ns

* Load = 30pF