VDIP2 Vinculum VNC1L Prototyping Module

Datasheet Version 0.91

© Future Technology Devices Intl Ltd. 2006-2007

Page 

2.�� �PI Inter�a�e �igna�� �es�riptions and Timing �iagrams

2.���PIInter�a�e�igna���es�riptionsandTiming�iagrams

Table 8 - Data and Control Bus Signal Mode Options - SPI Interface

Pin No.

Name

Type

Description

14

SCLK

Input

SPI Clock input, 12MHz maximum.

16

SDI

Input

SPI Serial Data Input

17

SDO

Output

SPI Serial Data Output

18

CS

Input

SPI Chip Select Input

Figure 5 - SPI Slave Data Read Cycle

SPICLK

SPI Data In

SPI Data Out

SPI CS

R/W ADD

D0

D1

D2

D3

D4

D5

D6

D7

1

1

0

From Start - SPI CS must be held high for the entire read cycle, and must be taken low for at least one clock period

afterthereadiscompleted.ThefirstbitonSPIDataInistheR/Wbit-inputtinga‘1’hereallowsdatatobereadfrom

the chip. The next bit is the address bit, ADD, which is used to indicate whether the data register (‘0’) or the status

register (‘1’) is read from. During the SPI read cycle a byte of data will start being output on SPI Data Out on the next

clockcycleaftertheaddressbit,MSBfirst.Afterthedatahasbeenclockedoutofthechip,thestatusofSPIData

Out should be checked to see if the data read is new data. A ‘0’ level here on SPI Data Out means that the data read

is new data. A ‘1’ indicates that the data read is old data, and the read cycle should be repeated to get new data.

Remember that CS must be held low for at least one clock period before being taken high again to continue with the

next read or write cycle.

Figure 6 - SPI Slave Data Write Cycle

SPICLK

SPI Data In

SPI Data Out

SPI CS

R/W ADD

D0

D1

D2

D3

D4

D5

D6

D7

1

0

0

From Start - SPI CS must be held high for the entire write cycle, and must be taken low for at least one clock period

afterthewriteiscompleted.ThefirstbitonSPIDataInistheR/Wbit-inputtinga‘0’hereallowsdatatobewritten

to the chip. The next bit is the address bit, ADD, which is used to indicate whether the data register (‘0’) or the status