VDIP2 Vinculum VNC1L Prototyping Module

Datasheet Version 0.91

© Future Technology Devices Intl Ltd. 2006-2007

Page 10

register (‘1’) is written to. During the SPI write cycle a byte of data can be input to SPI Data In on the next clock cycle

aftertheaddressbit,MSBfirst.Afterthedatahasbeenclockedintothechip,thestatusofSPIDataOutshouldbe

checked to see if the data read was accepted. A ‘0’ level on SPI Data Out means that the data write was accepted. A

‘1’ indicates that the internal buffer is full, and the write should be repeated. Remember that CS must be held low for at

least one clock period before being taken high again to continue with the next read or write cycle.

Figure 7 - SPI Slave Data Timing Diagrams

T1

T2

T3

T4

T5

T6

T7

SPICLK

SPICS /

SPI DATA IN

SPI DATA OUT

Table 9 - SPI Slave Data Timing

Time

Description

Min

Typical Max

Unit

T1

SPICLK Period

83

-

-

ns

T2

SPICLK High

20

-

-

ns

T3

SPICLK Low

20

-

-

ns

T4

Input Setup Time

10

-

-

ns

T5

Input Hold Time

10

-

-

ns

T6

Output Hold Time

2

-

-

ns

T7

Output Valid Time

-

-

20

ns

Table 10 - Status Register (ADD = ‘1’)

Bit

Description

0

RXF#

1

TXE#

2

-

3

-

4

RXFIRQEn

5

TXEIRQEn

6

-

7

-