T48C862-R8 datasheet(75/107 Pages) ATMEL

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T48C862-R8

4590B–4BMCU–02/03

Figure 71. SSI Output Masking Function

Serial Interface Registers

Serial Interface Control

Auxiliary register address: "9"hex

Note: This bit has to be set to "1" during the MCL mode and the Timer 3 mode 10 or 11

•

In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been

loaded (SRDY = 1).

•

Setting SIR-bit loads the contents of the shift register into the receive buffer

(synchronous 8-bit mode only).

•

In MCL modes, writing a 0 to SIR generates a start condition and writing a 1

generates a stop condition.

8-bit shift register

MSB

LSB

Shift_CL

Control

Timer 2

Output

SSI-control

Compare 2/1

4-bit counter 2/1

CL2/1

SCL

CM1

OMSK

TOG2

POUT

T1OUT

SYSCL

Bit 3Bit 2Bit 1Bit 0

SIR

SCD

SCS1

SCS0

Reset value: 1111b

SIR

Serial Interface Reset

SIR = 1, SSI inactive

SIR = 0, SSI active

SCD

Serial Clock Direction

SCD = 1, SC line used as output

SCD = 0, SC line used as input

SCS1

Serial Clock source Select bit 1

SCS1

SCS0

Internal Clock for SSI

SCS0

Serial Clock source Select bit 0

SYSCL/2

T1OUT/2

Note: with SCD = 0 the bits SCS1

POUT/2

and SCS0 are insignificant

TOG2/2

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