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ADL5902

Data Sheet

Rev. B | Page 18 of 28

Compensating the device for temperature drift using TADJ allows

for great flexibility. If the user requires minimum temperature

drift at a given input power, a subset of the dynamic range, or

even over a different temperature range than shown in this data

sheet, the VTADJ can be swept while monitoring VOUT over the

temperature at the frequency and amplitude of interest. The

optimal VTADJ to achieve minimum temperature drift at a given

power and frequency is the value of VTADJ where the output has

minimum movement.

2.73

2.75

2.77

2.79

2.81

2.83

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

+125°C

+105°C

+85°C

+55°C

+25°C

–20°C

–40°C

0°C

VTADJ (V)

Figure 40. Effect of VTADJ at Various Temperatures, 2.14 GHz, −10 dBm

Varying VTADJ has only a very slight effect on VOUT at device

temperatures near 25°C; however, the compensation circuit

has more and more effect as the temperature departs farther

from 25°C.

The TADJ pin has a high input impedance and can be conven-

iently driven from an external source or from an attenuated value

of VREF using a resistor divider. Table 4 gives suggested voltage

divider values to generate the required voltage from VREF. The

resistors are shown in the evaluation board schematic (see

Figure 54). VREF does change slightly with temperature and also

input RF amplitude; however, the amount of change is unlikely

to result in a significant effect on the final temperature stability

of the RF measurement system. Typically, the temperature comp-

ensation circuit responds only to voltages between 0 and VS/2,

or about 2.5 V when VS = 5 V.

Figure 41 in the Power-Down Interface section shows a simpli-

fied schematic representation of the TADJ/PWDN interface.

POWER-DOWN INTERFACE

The quiescent and disabled currents for the ADL5902 at 25°C

are approximately 73 mA and 300 μA, respectively. The dual

function TADJ/PWDN pin is connected to the temperature comp-

ensation circuit as well as the power-down circuit. Typically, the

temperature compensation circuit responds only to voltages

between 0 and VS/2, or about 2.5 V when VS = 5 V.

When the voltage on this pin is greater than VS − 0.1 V, the device

is fully powered down. Figure 32 shows this characteristic as a

function of VPWDN. Note that, because of the design of this section

of the ADL5902, as VPWDN passes through a narrow range at

~4.5 V (or ~VS − 0.5 V), the TADJ/PWDN pin sinks approximately

500 μA. The source used to disable the ADL5902 must have a

sufficiently high current capability for this reason. Figure 33

shows the typical response times for various RF input levels.

The output reaches within 0.1 dB of the steady-state value in

approximately 5 μs; however, the reference voltage is available to

full accuracy in a much shorter time. This wake-up response

varies depending on the input coupling and CLPF.

TADJ/

PWDN

COMM

VPOS

200Ω

7kΩ

VREF

INTERCEPT

TEMPERATURE

COMPENSATION

200Ω

POWER-UP

CIRCUIT

SHUTDOWN

CIRCUIT

ESD

Figure 41. TADJ/PWDN Interface Simplified Schematic

VSET INTERFACE

The VSET interface has a high input impedance of 72 kΩ. The

voltage at VSET is converted to an internal current used to set

the internal VGA gain. The VGA attenuation control is approx-

imately 19 dB/V.

ACOM

2.5kΩ

18kΩ

VSET

GAIN ADJUST

54kΩ

Figure 42. VSET Interface Simplified Schematic

OUTPUT INTERFACE

The ADL5902 incorporates rail-to-rail output drivers with pull-

up and pull-down capabilities. The closed-loop, − 3dB bandwidth

from the input of the output amplifier to the output with no load is

approximately 58 MHz with a single-pole roll off of approximately

−20 dB/decade. The output noise is approximately 25 nV/√Hz

at 100 kHz. The VOUT pin can source and sink up to 10 mA.

There is also an internal load from VOUT to COMM of 2500 Ω.

VOUT

CLPF

2kΩ

500Ω

2pF

ESD

VPOS

COMM

Figure 43. VOUT Interface Simplified Schematic

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