ADL5906ACPZN-R7 datasheet(18/30 Pages) AD

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Data Sheet

ADL5906

THEORY OF OPERATION

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Rev. B | 18 of 30

TEMPERATURE COMPENSATION INTERFACE

The ADL5906 has a TADJ pin that provides the ability to optimize

temperature performance using proprietary techniques as in the

ADL5902. Just like the ADL5902, the ADL5906 has dual function-

ality on Pin 1, TADJ/PWDN; however, the PWDN function was

redesigned to be driven by CMOS logic as low as 1.8 V. For more

detail on the power-down interface, see the Power-Down Interface

section.

For optimal performance, the output temperature drift must be com-

pensated using the TADJ pin. The absolute value of compensation

varies with frequency and VTGT. For recommended VTADJ values at

popular frequencies, see the Setting VTADJ section.

One difference in the temperature compensation of the ADL5906

compared to the ADL5902 is that VTADJ adjusts the slope of the

detector, and with the ADL5902, the intercept was adjusted. Adjust-

ing the slope was found beneficial to locking in temperature drift

and thereby producing parallel error curves over most frequencies.

Any remaining intercept temperature drift can then be reduced in

the digital domain after sampling VRMS because the intercept drift is

quite repeatable at frequencies up to approximately 5.8 GHz (see

the Using VTEMP to Improve Intercept Temperature Drift section).

There is a trade-off in setting values, and optimizing for one area

of the dynamic range may mean less than optimal drift performance

at other input amplitudes. In addition, different voltages applied

to the VTGT pin impact drift; all TADJ voltages shown in the

performance curves were determined with a VTGT of 0.8 V. For

VTGT values that do not deviate too far from the nominal 0.8 V, and

for frequencies up to approximately 5 GHz, it is expected that the

TADJ voltages are a good starting point for the best temperature

drift compensation.

Compensating the device for temperature drift using VTADJ allows

for great flexibility. If the user requires minimum temperature drift at

a given input power, a subset of the dynamic range, or even over a

different temperature range than shown in this data sheet, the VTADJ

can be swept while monitoring VRMS over the temperature at the

frequency and amplitude of interest. The optimal VTADJ to achieve

minimum temperature drift at a given power and frequency is the

value of VTADJ where the output has minimum movement.

Figure 45. Effect of VTADJ at Various Temperatures, 2.14 GHz, 0 dBm

Varying VTADJ has only a very slight effect on VRMS at device

temperatures near 25°C; however, the compensation circuit has

increasing effect as the temperature departs farther from 25°C.

It is important to note that the slope is adjusted vs. temperature.

The pivot point of this is at low input power levels and thereby

moves the VRMS output more at larger input signal levels; that is,

near maximum input power, the temperature drift can be minimized

the most. This is advantageous in most power measurement cases

because errors at larger powers tend to have more of a negative

effect.

The TADJ/PWDN pin has a nominal input resistance of 70 kΩ and

can be conveniently driven from an external source or from an

attenuated value of VREF using a resistor divider. The resistors

are shown in the evaluation board schematic (see Figure 63). The

voltage range for VTADJ is from 0 V to approximately 1.0 V because

approximately 1.3 V is the logic threshold for power down of the

device.

POWER-DOWN INTERFACE

Figure 46 shows a simplified schematic representation of the TADJ/

PWDN interface.

The quiescent and power-down currents for the ADL5906 at 25°C

are approximately 68 mA and 250 µA, respectively. The dual

function TADJ/PWDN pin is connected to the temperature compen-

sation circuit as well as the power-down circuit. The temperature

compensation circuit responds only to voltages between 0 V and 1

V. When the voltage on this pin is greater than ~1.4 V, the device

is fully powered down. Figure 38 shows this characteristic as a

function of VPWDN. The TADJ/PWDN pin with an internal 70 kΩ

resistor to ground sinks approximately 26 µA at 1.8 V, 47 µA at

3.3 V, and 72 µA at 5 V. The source used to disable the ADL5906

must have a sufficiently high current capability for this reason.

Figure 31 shows the typical response times for various RF input

levels. The output reaches within 1 dB of its steady state value

in approximately 12 µs for CRMS = 1 nF; however, the reference

voltage is available to full accuracy in a much shorter time. This

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