Data Sheet

AD8318

USING THE AD8318

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Rev. E | 12 of 24

BASIC CONNECTIONS

The AD8318 is specified for operation up to 8 GHz. As a result, low

impedance supply pins with adequate isolation between functions

are essential. In the AD8318, VPSI and VPSO, the two positive

supply pins, must be connected to the same positive potential.

The VPSI pin biases the input circuitry, while the VPSO pin biases

the low noise output driver for VOUT. Separate commons are also

included in the device. CMOP is used as the common for the output

drivers. Connect Pin CMIP and Pin CMOP to a low impedance

ground plane.

Apply a power supply voltage of between 4.5 V and 5.5 V to

VPSO and VPSI. In addition, 100 pF and 0.1 μF power supply

decoupling capacitors connect close to each power supply pin. The

two adjacent VPSI pins can share a pair of decoupling capacitors

due to their proximity.

Figure 23. Basic Connections

The paddle of the AD8318 LFCSP is internally connected to CMIP.

For optimum thermal and electrical performance, solder the paddle

to a low impedance ground plane.

ENABLE INTERFACE

To enable the AD8318, the ENBL pin must be pulled high. Taking

ENBL low puts the AD8318 in sleep mode, reducing current con-

sumption to 260 µA at ambient. The voltage on ENBL must be

greater than 2 VBE (~1.7 V) to enable the device. When enabled,

the ENBL pin draws less than 1 µA. When ENBL is pulled low, the

pin sources 15 µA.

The enable interface has high input impedance. An internal 200 Ω

resistor is placed in series with the ENBL input for added protection.

Figure 24 depicts a simplified schematic of the enable interface.

The response time of the AD8318 ENBL interface is shown in

Figure 25.

Figure 24. ENBL Interface

Figure 25. ENBL Response Time; VPOS = 5.0 V; Input AC-Coupling Caps = 18

pF; CLPF = Open

INPUT SIGNAL COUPLING

The RF input to the AD8318 (INHI) is single ended and must be

ac-coupled. INLO (input common) must be ac-coupled to ground

(see Figure 23). Suggested coupling capacitors are 1 nF ceramic,

0402-style capacitors for input frequencies of 1 MHz to 8 GHz. The

coupling capacitors must be mounted close to the INHI pin and the

INLO pin. These capacitor values can be increased to lower the

input stage high-pass cutoff frequency. The high-pass corner is set

by the input coupling capacitors and the internal 10 pF capacitor.

The dc voltage on INHI and INLO is approximately one diode

voltage drop below the voltage applied to the VPSI pin.

The Smith Chart in Figure 16 shows the AD8318 input impedance

vs. frequency. Table 4 lists the reflection coefficient and impedance

at select frequencies. For Figure 16 and Table 4, the 52.3 Ω input

termination resistor is removed. At dc, the resistance is typically 2

kΩ. At frequencies up to 1 GHz, the impedance is approximated

as 1000 Ω||0.7 pF. The RF input pins are coupled to a network as

shown in the simplified schematic in Figure 26.