Data Sheet

AD8318

USING THE AD8318

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Rev. E | 13 of 24

Figure 26. Input Interface

While the input can be reactively matched, this is typically not nec-

essary. An external 52.3 Ω shunt resistor (connected on the signal

side of the input coupling capacitors, see Figure 23) combines

with the relatively high input impedance to provide an adequate

broadband 50 Ω match.

Table 4. Input Impedance for Select Frequency

Frequency (MHz)

S11

Impedance Ω (Series)

Real

Imaginary

100

+0.918

−0.041

927-j491

450

+0.905

−0.183

173-j430

900

+0.834

−0.350

61-j233

1900

+0.605

−0.595

28-j117

2200

+0.524

−0.616

28-j102

3600

+0.070

−0.601

26-j49

5300

−0.369

−0.305

20-j16

5800

−0.326

−0.286

22-j16

8000

−0.390

−0.062

22-j3

The coupling time constant, 50 × CC/2, forms a high-pass corner

with a 3 dB attenuation at fHP = 1/(2π × 50 × CC), where C1 =

C2 = CC. Using the typical value of 1 nF, this high-pass corner

is ~3.2 MHz. In high frequency applications, fHP must be as large

as possible to minimize the coupling of unwanted low frequency

signals. Likewise, in low frequency applications, a simple RC net-

work forming a low-pass filter must be added, generally placed at

the generator side of the coupling capacitors, thereby lowering the

required capacitance value for a given high-pass corner frequency.

OUTPUT INTERFACE

The logarithmic output interface is shown in Figure 27. The VOUT

pin is driven by a PNP output stage. An internal 10 Ω resistor is

placed in series with the emitter follower output and the VOUT

pin. The rise time of the output is limited mainly by the slew on

CLPF. The fall time is an RC limited slew provided by the load

capacitance and the pull-down resistance at VOUT. There is an

internal pull-down resistor of 350 Ω. Any resistive load at VOUT is

placed in parallel with the internal pull-down resistor and provides

additional discharge current.

Figure 27. Output Interface

SETPOINT INTERFACE

The setpoint interface is shown in Figure 28. The VSET input

drives the high impedance (250 kΩ) input of an internal operational

amplifier. The VSET voltage appears across the internal 3.13 kΩ

resistor to generate ISET. When a portion of VOUT is applied to

VSET, the feedback loop forces

−ID × log10(VIN/VINTERCEPT) = ISET

(2)

If VSET = VOUT/X, ISET = VOUT/(X × 3.13 kΩ). The result is VOUT =

(−ID × 3.13 kΩ × X) × log10(VIN/VINTERCEPT).

Figure 28. VSET Interface

The slope is given by −ID × X × 3.13 kΩ = −500 mV × X. For

example, if a resistor divider to ground is used to generate a VSET

voltage of VOUT/2, X = 2. The slope is set to −1 V/decade or −50

mV/dB.

TEMPERATURE COMPENSATION OF OUTPUT

VOLTAGE

The AD8318 functionality includes the capability to externally trim

the temperature drift. Attaching a ground-referenced resistor to the

TADJ pin alters an internal current, minimizing intercept drift vs.

temperature. As a result, the RTADJ can be optimized for operation

at different frequencies.

Figure 29. TADJ Interface