Data Sheet

ADL5506

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. C | 7 of 22

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Ball Grid Crd. Mnemonic

Description

1

A1

CFLT

Connection for an External Capacitor, CFLT, to Reduce the Modulation Content from the Output Voltage. It also slows the

response of the output and reduces the noise seen on the output. The capacitor is connected between CFLT and VLOG. See

the Filter Capacitor section for choosing the correct CFLT value.

2

B1

VPOS

Positive Supply. The positive supply voltage (VPOS) range is from 2.5 V to 5.5 V. Use decoupling capacitors near this pin on the

printed circuit board.

3

C1

RFIN

RF Input. 5 pF ac coupling capacitor on chip. Connect a 52.3 Ω shunt resistor near this pin for broadband 50 Ω match. See the

Input Coupling Options section for more matching options.

4

C2

COMM

Device Common (Ground). Connect this pin to system ground using a low impedance path.

5

B2

VLOG

Logarithmic Output. The output voltage (VLog) increases with increasing input amplitude. The output is proportional to the

logarithm of the input signal level.

6

A2

ENBL

Device Enable. Connect the ENBL pin to a logic high (1.2 V to VPOS) to enable the device. Connect the ENBL pin to a logic low

(0 V to 0.5 V) to disable the device.