Data Sheet

ADL5506

APPLICATIONS INFORMATION

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Rev. C | 19 of 22

of the decibel value of the intercept shift (18.5 mV/dB × 1.5 dB) to

the output voltage of the ADL5506.

Temperature Drift at High Frequencies

Figure 23 and Figure 27 show the log slope and error over temper-

ature for a 3.5 GHz and 4.5 GHz input signal, respectively. Error

due to drift over temperature consistently remains within ±0.5 dB

for a temperature range of 0°C to 85°C. Temperatures below 0°C

begin to exhibit error beyond 0.5 dB with error becoming no worse

than −3 dB typical at −40°C. For all frequencies using a reduced

temperature range, higher measurement accuracy is achievable.

Operation Above 4.5 GHz

The ADL5506 works at high frequencies but exhibits slightly higher

output voltage temperature drift, especially at cold temperatures as

described in the Temperature Drift at High Frequencies section.

Figure 49 and Figure 50 show VLOG vs. PIN over frequency from

30 MHz to 6 GHz. The ADL5506 exhibits a significant intercept

shift, high power ripple, and a continued decrease of the slope,

which all contribute to a decrease in dynamic range. The changes

in performance that occur as frequency is increased is partly due to

less energy transferring into the device and partly to the bandwidth

limitation of the limiting amplifier stages.

Figure 49. VLOG vs. PIN over Frequency (30 MHz to 4500 MHz)

Figure 50. VLOG vs. PIN over Frequency (4.5 GHz to 6 GHz)

VLOG Output Noise

The ADL5506 VLOG output noise is shown in Figure 31 in the

Typical Performance Characteristics section for Capacitor CFLT =

open. Placing capacitance from CFLT to VLOG decreases the

noise spectral density and the integrated noise. The choice of the

CFLT value depends on the requirements pertaining to integrated

noise and noise spectral density at a given frequency. Also, the

value of CFLT directly controls the video bandwidth of the output,

and thus controls the output response time to an RF pulse (see the

VLOG Pulse Response Time section).

VLOG Pulse Response Time

The ADL5506 VLOG output response for rise and fall times to a

given RF input pulse is quickest for CFLT = open; that is, the only

capacitance on the CFLT node is the internal capacitor. Adding

off-chip capacitance from the CFLT pin to the VLOG pin decreases

the video bandwidth and slows the output response to an RF input

pulse. See the Filter Capacitor section for an approximate closed

form equation for the VLOG video bandwidth.

Figure 28 shows the response time when the ENBL pin is pulsed

while having the VPOS pin connect to a 3.0 V supply and an RF

signal applied at RFIN. The sharp pulse that is seen on VLOG

preceding the actual response of the detectors, which happens

approximately 0.5 µs later, is the power-up transient that occurs

in the output stage. The upper voltage limit of these power-up

transients is 2.25 V typical, for a 3.0 V supply. Ensure that these

power-up transients do not overload the circuit that the VLOG pin

drives.

Device Handling

The wafer level chip scale package consists of solder bumps

connected to the active side of the die. The device is lead-free with

95.5% tin, 4.0% silver, and 0.5% copper solder bump composition.

The WLCSP package can be mounted on printed circuit boards

using standard surface-mount assembly techniques; however, take