Data Sheet

ADL5506

APPLICATIONS INFORMATION

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Rev. C | 17 of 22

When more than two calibration points are chosen to compute

the error, the error computation must be done in a piece-wise

fashion. For the ADL5506, three calibration points were chosen

in characterization to compute the log conformance error of the

ADL5506. For example, one set of calibration points used was

−40 dBm, −30 dBm, and −10 dBm. With three calibration points,

two regions of error are computed, Region A and Region B (see

Figure 45) To compute the error, first compute two slopes and two

intercepts: one slope and intercept for Region A and the other slope

and intercept for Region B. Note that the error is zero at each

calibration point.

IN1

IN2

LOG1

LOG2

A

SLOPE

P

P

V

V

V







_

(5)

IN2

IN3

LOG2

LOG3

B

SLOPE

P

P

V

V

V







_

(6)

Next, find the two intercepts. (The two intercept points can be

computed with the same calibration points, middle point for both,

with the slope being different for the two intercept points.)

IN2

A

SLOPE

LOG

A

O

P

V

V

P





_

2

_

(7)

3

_

3

_

IN

B

SLOPE

LOG

B

O

P

V

V

P





(8)

Figure 44. VLOG vs. PIN

The log conformance error for Region A, which is from the low end

of the input power range to PIN2 is as follows:

A

O

IN

A

SLOPE

IN

LOG

IN

A

P

P

V

P

V

P

Error

_

_

)

(

)

(







(9)

The log conformance error for Region B, which is from PIN2 to the

upper end of the input power range is as follows:

B

O

IN

B

SLOPE

IN

LOG

IN

B

P

P

V

P

V

P

Error

_

_

)

(

)

(







(10)

Figure 45. Error vs. PIN

For four calibration points, there are three regions of error comput-

ed.

Filter Capacitor

The video bandwidth of VLOG is approximately 3.5 MHz. In CW

applications where the input frequency is much higher than this, no

further filtering of the demodulated signal is required. Where there

is a low frequency modulation of the carrier amplitude, however,

reduce the low-pass corner by the addition of an external filter

capacitor, CFLT. The video bandwidth is related to CFLT by

Video

 Bandwidtℎ =  1

2π ×

 13 kΩ × 3.5 pF + CF (11)

Input Coupling Options

The internal 5 pF coupling capacitor of the ADL5506, along with

the low frequency input impedance of 1.7 kΩ, gives a high-pass

input corner frequency of approximately 19 MHz. This sets the

minimum operating frequency. Figure 46 to Figure 48 show three

options for input coupling. A broadband resistive match can be

implemented by connecting a shunt resistor to ground at RFIN (see

Figure 46). This 52.3 Ω resistor (other values can also be used to

select different overall input impedances) combines with the input

impedance of the ADL5506 to give a broadband input impedance

of 50 Ω. While the input resistance and capacitance (RIN and

CIN) varies by a maximum of approximately ±20% from device to

device, the dominance of the external shunt resistor means that the

variation in the overall input impedance is close to the tolerance of

the external resistor. Achieve better return loss by placing the 52.3

Ω shunt resistor as near the device under test (DUT) as possible.

A reactive match can also be implemented, as shown in Figure

47. This is not recommended at low frequencies because device

tolerances dramatically vary the quality of the match due to the