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ADL5513ACPZ-R2 数据表(PDF) 13 Page - Analog Devices

部件名 ADL5513ACPZ-R2
功能描述  1 MHz to 4 GHz, 80 dB Logarithmic Detector/Controller
PDF  25 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL5513ACPZ-R2 数据表(HTML) 13 Page - Analog Devices

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Data Sheet
ADL5513
THEORY OF OPERATION
analog.com
Rev. B | 13 of 25
The ADL5513 is a demodulating logarithmic amplifier, specifically
designed for use in RF measurement and power control applica-
tions at frequencies up to 4 GHz. A block diagram is shown in
Figure 24. Sharing much of its design with the AD8313 logarithmic
detector/controller, the ADL5513 maintains tight intercept variability
vs. temperature over a 80 dB range. Additional enhancements over
the AD8313, such as a reduced RF burst response time of 20 ns
and board space requirements of only 3 mm × 3 mm, add to the low
cost and high performance benefits found in the ADL5513.
Figure 24. Block Diagram
A fully differential design, using a proprietary, high speed SiGe
process, extends high frequency performance. The maximum input
with ±1 dB log conformance error is typically 10 dBm (referred
to 50 Ω). The noise spectral density of −70 dBm sets the lower
limit of the dynamic range. The common pin, COMM, provides a
quality low impedance connection to the printed circuit board (PCB)
ground. The package paddle, which is internally connected to the
COMM pin, should also be grounded to the PCB to reduce thermal
impedance from the die to the PCB.
The logarithmic function is approximated in a piecewise fashion by
cascaded gain stages. (For a more comprehensive explanation of
the logarithm approximation, see the AD8307 data sheet.) Using
precision biasing, the gain is stabilized over temperature and supply
variations. The overall dc gain is high, due to the cascaded nature
of the gain stages.
The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
After the detector currents are summed and filtered, the following
function is formed at the summing node:
ID × log10(VIN/VINTERCEPT)
(1)
where:
ID is the internally set detector current.
VIN is the input signal voltage.
VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
the output voltage is 0 V, if it were capable of going to 0).



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