Data Sheet

ADL5513

APPLICATIONS INFORMATION

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Rev. B | 14 of 25

BASIC CONNECTIONS

The ADL5513 is specified for operation up to 4 GHz; as a result,

low impedance supply pins with adequate isolation between func-

tions are essential. A power supply voltage of between 2.7 V and

5.5 V should be applied to VPOS. Connect 100 pF and 0.1 µF

power supply decoupling capacitors close to this power supply pin.

Figure 25. Basic Connections

The exposed paddle of the LFCSP package is internally connected

to COMM. For optimum thermal and electrical performance, solder

the paddle to a low impedance ground plane.

INPUT SIGNAL COUPLING

The RF input (INHI) is single-ended and must be ac-coupled. INLO

(input common) should be ac-coupled to ground. Suggested cou-

pling capacitors are 47 nF, ceramic, 0402-style capacitors for input

frequencies of 1 MHz to 4 GHz. The coupling capacitors should be

mounted close to the INHI and INLO pins. The coupling capacitor

values can be increased to lower the high-pass cutoff frequency of

the input stage. The high-pass corner is set by the input coupling

capacitors and the internal 20 pF high-pass capacitor. The dc

voltage on INHI and INLO is about one diode voltage drop below

VPOS.

Figure 26. Input Interface

While the input can be reactively matched, in general, this is not

necessary. An external 52.3 Ω shunt resistor (connected to the

signal side of the input coupling capacitors, as shown in Figure 25)

combines with relatively high input impedance to give an adequate

broadband 50 Ω match.

The coupling time constant, 50 × CC/2, forms a high-pass corner

with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 =

C2 = CC. Using the typical value of 47 nF, this high-pass corner

is ~68 kHz. In high frequency applications, fHP should be as large

as possible to minimize the coupling of unwanted low frequency

signals. In low frequency applications, a simple RC network forming

a low-pass filter should be added at the input for similar reasons.

This low-pass filter network should generally be placed at the

generator side of the coupling capacitors, thereby lowering the

required capacitance value for a given high-pass corner frequency.

OUTPUT FILTERING

For applications in which maximum video bandwidth and, conse-

quently, fast rise time are desired, it is essential that the CLPF pin

be left unconnected and free of any stray capacitance.

The output video bandwidth, which is 10 MHz, can be reduced by

connecting a ground-referenced capacitor (CFLT) to the CLPF pin,

as shown in Figure 27. This is generally done to reduce output

ripple (at twice the input frequency for a symmetricinput waveform

such as sinusoidal signals).

Figure 27. Lowering the Postdemodulation Bandwidth

CFLT is selected by

CFLT= 1

2π×1 kΩ×Video

 Bandwidtℎ

−3.0 pF (2)

The video bandwidth should typically be set to a frequency equal to

about one-tenth the minimum input frequency. This ensures that the

output ripple of the demodulated log output, which is at twice the

input frequency, is well filtered.

In many log amp applications, it may be necessary to lower the

corner frequency of the postdemodulation filter to achieve low

output ripple while maintaining a rapid response time to changes in

signal level. An example of a four-pole active filter is shown in the

AD8307 data sheet. Averaging the output measurement can also

be done when filtering is not possible.

OUTPUT INTERFACE

The VOUT pin is driven by a PNP output stage. An internal 10 Ω

resistor is placed in series with the output and the VOUT pin. The

rise time of the output is limited mainly by the slew on CLPF. The

fall time is an RC-limited slew given by the load capacitance and