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TDA4AEN...Q1 数据表(PDF) 110 Page - Texas Instruments |
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TDA4AEN...Q1 数据表(HTML) 110 Page - Texas Instruments |
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110 / 236 page  Table 6-20. Clock Switching Characteristics see Figure 6-15 NO. PARAMETER MIN MAX UNIT CLK4 tc(SYSCLKOUT0) Cycle time minimum,SYSCLKOUT0 8 ns CLK5 tw(SYSCLKOUT0H) Pulse Duration, SYSCLKOUT0 high A*0.4(1) A*0.6(1) ns CLK6 tw(SYSCLKOUT0L) Pulse Duration, SYSCLKOUT0 low A*0.4(1) A*0.6(1) ns CLK4 tc(OBSCLK0) Cycle time minimum, OBSCLK0 5 ns CLK5 tw(OBSCLK0H) Pulse Duration, OBSCLK0 high B*0.45(2) B*0.55(2) ns CLK6 tw(OBSCLK0L) Pulse Duration, OBSCLK0 low B*0.45(2) B*0.55(2) ns CLK4 tc(OBSCLK1) Cycle time minimum, OBSCLK1 5 ns CLK5 tw(OBSCLK1H) Pulse Duration, OBSCLK1 high F*0.45(3) F*0.55(3) ns CLK6 tw(OBSCLK1L) Pulse Duration, OBSCLK1 low F*0.45(3) F*0.55(3) ns CLK4 tc(CLKOUT0) Cycle time minimum, CLKOUT0 20 ns CLK5 tw(CLKOUT0H) Pulse Duration, CLKOUT0 high C*0.4(4) C*0.6(4) ns CLK6 tw(CLKOUT0L) Pulse Duration, CLKOUT0 low C*0.4(4) C*0.6(4) ns CLK4 tc(MCU_SYSCLKOUT0) Cycle time minimum, MCU_SYSCLKOUT0 10 ns CLK5 tw(MCU_SYSCLKOUT0H) Pulse Duration, MCU_SYSCLKOUT0 high E*0.4(5) E*0.6(5) ns CLK6 tw(MCU_SYSCLKOUT0L) Pulse Duration, MCU_SYSCLKOUT0 low E*0.4(5) E*0.6(5) ns CLK4 tc(MCU_OBSCLK0) Cycle time minimum, MCU_OBSCLK0 5 ns CLK5 tw(MCU_OBSCLK0H) Pulse Duration, MCU_OBSCLK0 high D*0.45(6) D*0.55(6) ns CLK6 tw(MCU_OBSCLK0L) Pulse Duration, MCU_OBSCLK0 low D*0.45(6) D*0.55(6) ns CLK4 tc(WKUP_CLKOUT0) Cycle time minimum, WKUP_CLKOUT0 5 ns CLK5 tw(WKUP_CLKOUT0H) Pulse Duration, WKUP_CLKOUT0 high W*0.4(7) W*0.6(7) ns CLK6 tw(WKUP_CLKOUT0L) Pulse Duration, WKUP_CLKOUT0 low W*0.4(7) W*0.6(7) ns CLK4 tc(AUDIO_EXT_REFCLK0 ) Cycle time minimum, AUDIO_EXT_REFCLK0 (McASP Clock Source) 20 ns Cycle time minimum, AUDIO_EXT_REFCLK0 (PLL Clock Source) 10 ns CLK5 tw(AUDIO_EXT_REFCLK0 H) Pulse Duration, AUDIO_EXT_REFCLK0 high G*0.4(8) G*0.6(8) ns CLK6 tw(AUDIO_EXT_REFCLK0 L) Pulse Duration, AUDIO_EXT_REFCLK0 low G*0.4(8) G*0.6(8) ns CLK4 tc(AUDIO_EXT_REFCLK1 ) Cycle time minimum, AUDIO_EXT_REFCLK1 (McASP Clock Source) 20 ns Cycle time minimum, AUDIO_EXT_REFCLK1 (PLL Clock Source) 10 ns CLK5 tw(AUDIO_EXT_REFCLK1 H) Pulse Duration, AUDIO_EXT_REFCLK1 high J*0.4(9) J*0.6(9) ns CLK6 tw(AUDIO_EXT_REFCLK1 L) Pulse Duration, AUDIO_EXT_REFCLK1 low J*0.4(9) J*0.6(9) ns (1) A = SYSCLKOUT0 cycle time in ns. (2) B = OBSCLK0 cycle time in ns. (3) F = OBSCLK1 cycle time in ns. (4) C = CLKOUT0 cycle time in ns. (5) E = MCU_SYSCLKOUT0 cycle time in ns. (6) D = MCU_OBSCLK0 cycle time in ns. (7) W = WKUP_CLKOUT0 cycle time in ns. (8) G = AUDIO_EXT_REFCLK0 cycle time in ns. (9) J = AUDIO_EXT_REFCLK1 cycle time in ns. Output Clock CLK4 CLK5 CLK6 Figure 6-15. Clock Switching Characteristics TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 110 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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