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TDA4AEN...Q1 数据表(PDF) 113 Page - Texas Instruments

部件名 TDA4AEN...Q1
功能描述  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4AEN...Q1 数据表(HTML) 113 Page - Texas Instruments

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Table 6-22. MCU_OSC0 Switching Characteristics - Crystal Mode (continued)
PARAMETER
MIN
TYP
MAX
UNIT
ts
Start-up Time
4
ms
VDDS_OSC0
MCU_OSC0_XO
t
sX
Time
VSS
VDDS_OSC0 (min.)
VDD_CORE (min.)
VSS
VDD_CORE
AM65x_MCU_OSC_STARTUP_02
Figure 6-17. MCU_OSC0 Start-up Time
6.9.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors
CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the
PCB designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in Table 6-22.
AM65x_MCU_OSC_CC_05
C
PCBXI
C
PCBXO
C
L1
C
L2
PCB
Signal Traces
Crystal Circuit
Components
MCU_OSC0_XO
MCU_OSC0_XI
C
XI
C
XO
Device
Figure 6-18. Load Capacitance
Load capacitors, CL1 and CL2 in Figure 6-16, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
www.ti.com
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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