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TDA4AEN...Q1 数据表(PDF) 131 Page - Texas Instruments |
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TDA4AEN...Q1 数据表(HTML) 131 Page - Texas Instruments |
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131 / 236 page  Table 6-42. CPTS Switching Characteristics see Figure 6-34 NO. PARAMETER DESCRIPTION SOURCE MIN MAX UNIT T6 tw(TS_COMPH) Pulse duration, TS_COMP high 36P(1) - 2 ns T7 tw(TS_COMPL) Pulse duration, TS_COMP low 36P(1) - 2 ns T8 tw(TS_SYNCH) Pulse duration, TS_SYNC high 36P(1) - 2 ns T9 tw(TS_SYNCL) Pulse duration, TS_SYNC low 36P(1) - 2 ns T10 tw(SYNC_OUTH) Pulse duration, SYNCn_OUT high TS_SYNC 36P(1) - 2 ns GENF 5P(1) - 2 ns T11 tw(SYNC_OUTL) Pulse duration, SYNCn_OUT low TS_SYNC 36P(1) - 2 ns GENF 5P(1) - 2 ns (1) P = functional clock period in ns. TS_COMP T6 T7 TS_SYNC T8 T9 SYNCn_OUT T10 T11 Figure 6-34. CPTS Switching Characteristics For more information, see Data Movement Architecture (DMA) chapter in the device TRM. 6.9.5.4 CSI-2 Note For more information, see the Camera Serial Interface Receiver (CSI_RX_IF) section in the device TRM. The CSI_RX_IF is connected to device port instances named CSIRXn, where n is the instance number. The CSI_RX_IF and associated D-PHY implements a CSI-2 port (CSIRX0) compliant with the MIPI D-PHY specification v1.2 and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock lane operating in synchronous double data rate mode. For CSI-2 timing details, see the respective MIPI specifications mentioned above. • Support for 1-, 2-, 3- or 4-lane data transfer modes up to 1.5Gbps 6.9.5.5 CSI-2 TX TBD www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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