TDA4AEN...Q1 datasheet(209/236 Pages) TI

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6.9.5.19.2.2 OSPI0 Tap DDR Timing

Table 6-124, Figure 6-106, Table 6-125, and Figure 6-107 present timing requirements and switching

characteristics for OSPI0 Tap DDR Mode.

Table 6-124. OSPI0 Timing Requirements – Tap DDR Mode

see Figure 6-106

NO.

MODE

MIN

MAX

UNIT

O13

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

No Loopback

(17.04 -

(0.975T(1)R(2)))

O14

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

No Loopback

(- 3.16 +

(0.975T(1)R(2)))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = reference clock cycle time in ns

OSPI_CLK

O14

O13

OSPI_TIMING_03

OSPI_D[i:0]

O14

O13

Figure 6-106. OSPI0 Timing Requirements – Tap DDR, No Loopback

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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