TDA4AEN...Q1 datasheet(212/236 Pages) TI

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6.9.5.22 UART

For more details about features and additional description information on the device Universal Asynchronous

Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description

sections.

Table 6-129. UART Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

30(1)

(1)

This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the

load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall

times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,

it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the

device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point

where the minimum data valid time of the attached device is violated.

Table 6-130. UART Timing Requirements

see Figure 6-109

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tw(RXD)

Pulse width, receive data bit high or low

0.95U(1)

(2)

1.05U(1)

(2)

tw(RXDS)

Pulse width, receive start bit low

0.95U(1)

(2)

(1)

U = UART baud time in ns = 1/programmed baud rate.

(2)

This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.

Table 6-131. UART Switching Characteristics

see Figure 6-109

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

f(baud)

Programmable baud rate for Main Domain UARTs

Mbps

Programmable baud rate for MCU and WKUP Domain UARTs

3.7

Mbps

tw(TXD)

Pulse width, transmit data bit high or low

U(1) - 2

U(1) + 2

tw(TXDS)

Pulse width, transmit start bit low

U(1) - 2

(1)

U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the

device TRM.

UARTi_TXD

Start

Bit

Data Bits

UARTi_RXD

Data Bits

Bit

Start

UART_TIMING_01_RCVRVIHVIL

Figure 6-109. UART Timing Requirements and Switching Characteristics

For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter

in the device TRM.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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