TDA4AEN...Q1 datasheet(210/236 Pages) TI

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Table 6-125. OSPI0 Switching Characteristics – Tap DDR Mode

see Figure 6-107

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

td(CSn-CLK)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) +

((0.975M(2)R(5)) - 1)

((0.525P(1)) +

( 1.025M(2)R(5)) + 1)

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(5)) - 1)

((0.525P(1)) +

(1.025N(3)R(5)) + 1)

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

(- 5.04 +

(0.975(T(4) + 1)R(5))

- (0.525P(1)))

(3.64 +

(1.025(T(4) + 1)R(5))

- (0.475P(1)))

(1)

P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]

(5)

R = reference clock cycle time in ns

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 6-107. OSPI0 Switching Characteristics – Tap DDR, No Loopback

6.9.5.20 PCIe

The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the

specification for timing details.

For more details about features and additional description information on the device Peripheral Component

Interconnect Express (PCIe), see the SERDES0 Signal Descriptions and the corresponding subsection within

Detailed Description.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter of the device TRM.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

210

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