Data Sheet

LT8349

analog.com

Rev B

7 of 29

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 3. Pin Descriptions

PIN

NAME

DESCRIPTION

A1

RT

A resistor is tied between RT and SGND to set the switching frequency.

A2

FB

Feedback Input Pin. This pin receives the feedback voltage from the external resistor

divider between VOUT and SGND. FB pin is one input to the error amplifier of the output

voltage control loop.

A3

VIN

Input Supply Pin. This pin provides supply for internal drivers and control circuits. This

pin must be decoupled with a 1µF minimum low ESR ceramic capacitor to the ground

plane. Place the VIN bypass capacitor close to the VIN pin.

A4

VC

Error Amplifier Output and Switching Regulator Compensation Pin. Connect this pin to

appropriate external components to compensate the regulator loop frequency

response.

A5

SGND

Signal Ground. Connect SGND to PGND on the PCB with low impedance.

B1

BST1

This pin is used to provide a gate drive voltage to the top side power switch of channel

1. Place a 0.1µF bootstrap capacitor between BST1 and SW1 pins and close to the IC.

B2

SYNC/MODE

External Synchronization Input and Mode Selection Pin. This pin allows five selectable

modes for optimization of performance.

Where the selectable modes of operation are:

Burst = low IQ, low output ripple operation at light loads

WLCSP PACKAGE

CB-35-4

1.845mm × 2.545mm × 0.455mm

JEDEC BOARD:

θJA = 38.7°C/W, θJB = 12.3°C/W,

DEMO BOARD:

θJA = 28.8°C/W, ΨJB = 11.8°C/W

LT8349

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

A

B

C

D

E

F

1

2

3

4

5

G

VIN

RT

SW2

SW2

SYNC

SW2

FB

PGND

VOUT

VOUT

VOUT

VOUT

BST1

SW1

SW1

SW1

PGND

PGND

PGND

EN

VC SGND

BST2

VOUT

SW1

SW2

ISET

VOUT

VOUT

VOUT

SW2

PGND

SW1

VOUT

VOUT