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LT8349ACBZ-R7 数据表(PDF) 18 Page - Analog Devices |
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LT8349ACBZ-R7 数据表(HTML) 18 Page - Analog Devices |
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18 / 29 page ![]() Data Sheet LT8349 analog.com Rev B 18 of 29 1.0 127 2.9 33.2 1.1 113 3.0 30.9 1.2 102 3.1 29.4 1.3 93.1 3.2 28.0 1.4 84.5 3.3 26.7 1.5 78.7 3.4 25.5 1.6 73.2 3.5 24.3 1.7 68.1 3.6 23.2 1.8 61.9 3.7 22.1 1.9 59.0 3.8 21.0 2.0 54.9 3.9 20.0 2.1 51.1 4.0 18.7 The operating frequency of the LT8349 can be synchronized to an external clock source with 100ns minimum pulse width. Figure 26 shows the external clock threshold (typ) required at the SYNC pin for synchronization. Figure 26. Sync/Mode Pin Logic Level (typ) vs Input Voltage By providing a digital clock signal to the SYNC/MODE pin, the IC operates at the half of the SYNC clock frequency and automatically enters FCM operation at light load. While in FCM the oscillator operates continuously, and the falling SW1 and SW2 transitions are aligned to the rising edges of the clock alternatively (180° out-of-phase), with a delay time of 80ns (typical). Figure 27 shows the synchronization between the SYNC/MODE pin input clock and the SW1 and SW2 transitions. If this feature is used, an RT resistor should be chosen to program switching frequency as close as possible to the SYNC pulse frequency. Figure 27. The synchronization between the SYNC/MODE pin input clock and the SW1 and SW2 transitions SYNC LOGIC HIGH SYNC LOGIC LOW INPUT VOLTAGE (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 tDELAY tDELAY SYNC INPUT SW1 SW2 tDELAY tDELAY |
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