405GPR datasheet(13/57 Pages) AMCC

13 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

Universal Interrupt Controller (UIC)

The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the

various sources of interrupts and the local PowerPC processor.

Features include:

• Supports 13 external and 19 internal interrupts

• Seven of the 13 interrupts are mapped to the same GPIOs as the PPC405GP.

• The other six interrupts can be mapped to any of the GPIOs.

• Edge triggered or level-sensitive

• Positive or negative active

• Non-critical or critical interrupt to processor core

• Programmable critical interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

10/100 Mbps Ethernet MAC

• Capable of handling full/half duplex 100Mbps and 10Mbps operation

• Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)

JTAG

• IEEE 1149.1 test access port

• IBM RISCWatch debugger support

• JTAG Boundary Scan Description Language (BSDL)

405GPR 数据表(PDF) 13 Page - Applied Micro Circuits Corporation