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PPC405GPR-3JB333 数据表(PDF) 31 Page - Applied Micro Circuits Corporation

部件名 PPC405GPR-3JB333
功能描述  Power PC 405GPr Embedded Processor
PDF  57 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

PPC405GPR-3JB333 数据表(HTML) 31 Page - Applied Micro Circuits Corporation

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405GPr – Power PC 405GPr Embedded Processor
AMCC
31
Revision 2.04 – September 7, 2007
Data Sheet
PCIGnt0[Req]
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
O
5V tolerant
3.3V PCI
PCIGnt1:5
Used as PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
Ethernet Interface
PHYRxD3:0
Received data. This is a nibble wide bus from the PHY. The data is
synchronous with the PHYRxClk.
I
5V tolerant
3.3V LVTTL
1
EMCTxD3:0
Transmit data. A nibble wide data bus towards the net. The data is
synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYRxErr
Receive Error. This signal comes from the PHY and is synchronous
to the PHYRxClk.
I
5V tolerant
3.3V LVTTL
1
PHYRxClk
Receiver Medium clock. This signal is generated by the PHY.
I
5V tolerant
3.3V LVTTL
1
PHYRxDV
Receive Data Valid. Data on the Data Bus is valid when this signal is
activated. Deassertion of this signal indicates end of the frame
reception.
I
5V tolerant
3.3V LVTTL
1
PHYCrS
Carrier Sense signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMCTxErr
Transmit Error. This signal is generated by the Ethernet controller, is
connected to the PHY and is synchronous with the PHYTxClk. It
informs the PHY that an error was detected.
O
5V tolerant
3.3V LVTTL
6
EMCTxEn
Transmit Enable. This signal is driven by the EMAC to the PHY. Data
is valid during the active state of this signal. Deassertion of this signal
indicates end of frame transmission. This signal is synchronous to
the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYTxClk
This clock comes from the PHY and is the Medium Transmit clock.
I
5V tolerant
3.3V LVTTL
1
PHYCol
Collision signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMCMDClk
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC].
Management information is transferred synchronously with respect to
this clock.
O
5V tolerant
3.3V LVTTL
EMCMDIO[PHYMDIO]
Management Data Input/Output is a bidirectional signal between the
Ethernet controller and the PHY. It is used to transfer control and
status information.
I/O
5V tolerant
3.3V LVTTL
1
Signal Functional Description (Sheet 2 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/O
Type
Notes



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