PPC405GPR-3JB333 datasheet(50/57 Pages) AMCC

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405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

I/O Specifications—Group 2

Notes:

1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM.

2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.

3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the PPC405GPr

IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,

and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

4. PerClk timing is specified with a 10pF load at the package pin. The indicated timing is valid only if PerClk feedback is

selected. Refer to the PowerPC 405GPr Embedded Processor User’s Manual for more information.

5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10% and

90% points of the output voltage.

6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

SDRAM Interface

BA1:0

4.5

1.6

15.3

10.2

MemClkOut

1, 2, 5

BankSel3:0

4.5

1.5

15.3

10.2

MemClkOut

2, 5

CAS

4.4

1.5

15.3

10.2

MemClkOut

1, 2, 5

ClkEn0:1

3.9

1.4

19.3

MemClkOut

2, 5

DQM0:3

4.5

1.4

15.3

10.2

MemClkOut

2, 5

DQMCB

4.3

1.4

15.3

10.2

MemClkOut

2, 5

ECC0:7

1.4

4.5

1.5

15.3

10.2

MemClkOut

2, 5

MemAddr12:0

4.6

1.5

15.3

10.2

MemClkOut

1, 2, 5

MemData0:31

1.4

5.1

1.4

15.3

10.2

MemClkOut

2, 5

RAS

4.4

1.5

15.3

10.2

MemClkOut

1, 2, 5

4.4

1.5

15.3

10.2

MemClkOut

1, 2, 5

External Slave Peripheral Interface

DMAAck0:3

6.1

2.2

10.3

7.1

PerClk

DMAReq0:3

3.2

PerClk

EOT0:3/TC0:3

6.4

10.3

7.1

PerClk

PerAddr0:31

2.2

7.1

15.3

10.2

PerClk

PerBLast

3.3

6.5

2.3

10.3

7.1

PerClk

PerCS0

PerCS1:7[GPIO10:16]

6.5

2.1

10.3

7.1

PerClk

PerData0:31

4.7

0.9

7.2

1.9

15.3

10.2

PerClk

PerOE

6.5

2.1

10.3

7.1

PerClk

PerPar0:3

2.3

7.2

2.1

15.3

10.2

PerClk

PerR/W

3.3

6.6

2.1

10.3

7.1

PerClk

PerReady

5.5

PerClk

PerWBE0:3

2.3

6.1

2.2

10.3

7.1

PerClk

External Master Peripheral Interface

BusReq

6.1

2.2

10.3

7.1

PerClk

ExtAck

5.9

2.1

10.3

7.1

PerClk

ExtReq

4.1

PerClk

ExtReset

15.3

10.2

PerClk

HoldAck

6.1

10.3

7.1

PerClk

HoldPri

2.1

nanana

PerClk

HoldReq

3.1

PerClk

0.7

-0.5

15.3

10.2

SysClk

4, 5

PerErr

2.4

PerClk

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PPC405GPR-3JB333 数据表(PDF) 50 Page - Applied Micro Circuits Corporation

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