PPC405GPR-3JB400 datasheet(36/57 Pages) AMCC

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405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

GPIO1[TS1E]

GPIO2[TS2E]

General Purpose I/O

Even Trace execution status. To access this function, software must

toggle a DCR bit.

I/O[O]

5V tolerant

3.3V LVTTL

1, 6

GPIO3[TS1O]

General Purpose I/O

Odd Trace execution status. To access this function, software must

toggle a DCR bit.

I/O[O]

5V tolerant

3.3V LVTTL

1, 6

GPIO4[TS2O]

General Purpose I/O

Odd Trace execution status. To access this function, software must

toggle a DCR bit.

I/O[O]

5V tolerant

3.3V LVTTL

1, 6

GPIO5:8[TS3:6]

General Purpose I/O

Trace status. To access this function, software must toggle a DCR

bit.

I/O[O]

5V tolerant

3.3V LVTTL

1, 6

GPIO9[TrcClk]

General Purpose I/O

Trace interface clock. A toggling signal that is always half of the CPU

core frequency. To access this function, software must toggle a DCR

bit.

Note: Initialization strapping must hold this pin low (0) during reset.

I/O[O]

5V tolerant

3.3V LVTTL

1, 6

GPIO24

General Purpose I/O.

Note: The pull-up initialization strapping resistor must be 1k

Ω rather

than 3k

Ω in order to overcome the internal pull-down resistor.

I/O

3.3V LVTTL

w/pull-down

1, 6

TestEn

Test Enable. Used only for manufacturing tests. Pull down for normal

operation.

1.8V CMOS

w/pull-down

TmrClk

An external clock input that can be used to clock the timers in the

CPU core.

5V tolerant

3.3V LVTTL

Trace Interface

[TS1E]GPIO1

[TS2E]GPIO2

Even Trace execution status. To access this function, software must

toggle a DCR bit

General Purpose I/O.

O[I/O]

5V tolerant

3.3V LVTTL

1, 6

[TS1O]GPIO3

Odd Trace execution status. To access this function, software must

toggle a DCR bit

General Purpose I/O.

O[I/O]

5V tolerant

3.3V LVTTL

1, 6

[TS2O]GPIO4

Odd Trace execution status. To access this function, software must

toggle a DCR bit

General Purpose I/O.

O[I/O]

5V tolerant

3.3V LVTTL

1, 6

[TS3:6]GPIO5:8

Trace status. To access this function, software must toggle a DCR bit

General Purpose I/O.

O[I/O]

5V tolerant

3.3V LVTTL

1, 6

Signal Functional Description (Sheet 7 of 8)

Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Bus Control Signals” on page 29.

Signal Name

Description

I/O

Type

Notes

PPC405GPR-3JB400 数据表(PDF) 36 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB400 数据表(HTML) 36 Page - Applied Micro Circuits Corporation

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数据表下载

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PPC405GPR-3JB400 数据表(PDF) 36 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB400 数据表(HTML) 36 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

数据表 下载

链接网址

数据表下载