PPC405GPR-3JB400Z datasheet(32/57 Pages) AMCC

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405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

SDRAM Interface

MemData0:31

Memory data bus.

Notes:

1. MemData0 is the most significant bit (msb).

2. MemData31 is the least significant bit (lsb).

I/O

3.3V LVTTL

MemAddr12:0

Memory address bus.

Notes:

1. MemAddr12 is the most significant bit (msb).

2. MemAddr0 is the least significant bit (lsb).

O3.3V LVTTL

BA1:0

Bank Address supporting up to 4 internal banks.

3.3V LVTTL

RAS

Row Address Strobe.

3.3V LVTTL

CAS

Column Address Strobe.

3.3V LVTTL

DQM0:3

DQM for byte lane: 0 (MemData0:7),

1 (MemData8:15),

2 (MemData16:23), and

3 (MemData24:31)

O3.3V LVTTL

DQMCB

DQM for ECC check bits.

3.3V LVTTL

ECC0:7

ECC check bits 0:7.

I/O

3.3V LVTTL

BankSel0:3

Select up to four external SDRAM banks.

3.3V LVTTL

Write Enable.

3.3V LVTTL

ClkEn0:1

SDRAM Clock Enable.

3.3V LVTTL

MemClkOut0:1

Two copies of an SDRAM clock allows, in some cases, glueless

SDRAM attach without requiring this signal to be repowered by a PLL

or zero-delay buffer.

O3.3V LVTTL

External Slave Peripheral Interface

PerData0:31

Peripheral data bus used by PPC405GPr when not in external

master mode, otherwise used by external master.

Note: PerData0 is the most significant bit (msb) on this bus.

I/O

5V tolerant

3.3V LVTTL

PerAddr0:31

Peripheral address bus used by PPC405GPr when not in external

master mode, otherwise used by external master.

Note: PerAddr0 is the most significant bit (msb) on this bus.

I/O

5V tolerant

3.3V LVTTL

PerPar0:3

Peripheral byte parity signals.

I/O

5V tolerant

3.3V LVTTL

PerWBE0:3

As outputs, these pins can act as byte-enables which are valid for an

entire cycle or as write-byte-enables which are valid for each byte on

each data transfer, allowing partial word transactions. As outputs,

pins are used by either the pripheral controller or the DMA controller

depending upon the type of transfer involved. Used as inputs when

an external bus master owns the external interface.

I/O

5V tolerant

3.3V LVTTL

1, 7

[PerWE]PCIINT

Peripheral write enable. Low when any of the four PerWBE0:3 write

byte enables are low.

PCI interrupt. Open-drain output (two states; 0 or open circuit)

5V tolerant

3.3V PCI

Signal Functional Description (Sheet 3 of 8)

Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Bus Control Signals” on page 29.

Signal Name

Description

I/O

Type

Notes

PPC405GPR-3JB400Z 数据表(PDF) 32 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB400Z 数据表(HTML) 32 Page - Applied Micro Circuits Corporation

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PPC405GPR-3JB400Z 数据表(PDF) 32 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB400Z 数据表(HTML) 32 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

数据表 下载

链接网址

数据表下载