PPC405GPR-3JB400Z datasheet(37/57 Pages) AMCC

37 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

[TrcClk]GPIO9

Trace interface clock. A toggling signal that is always half of the CPU

core frequency. To access this function, software must toggle a DCR

bit

General Purpose I/O.

Note: Initialization strapping must hold this pin low (0) during reset.

O[I/O]

5V tolerant

3.3V LVTTL

1, 6

Ground pins

GND

Ground

Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and

T11-T16 are also thermal balls.

OVDD pins

OVDD

Output driver voltage—3.3V.

VDD pins

VDD

Logic voltage—1.8V.

Other pins

Reserved

Reserved—Except for AF4, do not connect signals, voltage, or

ground to these pins. AF4 must be tied to OVDD or GND.

Signal Functional Description (Sheet 8 of 8)

Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Bus Control Signals” on page 29.

Signal Name

Description

I/O

Type

Notes

PPC405GPR-3JB400Z 数据表(PDF) 37 Page - Applied Micro Circuits Corporation

PPC405GPR-3JB400Z 数据表(HTML) 37 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

数据表下载