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PPC405GPR-3JB400Z 数据表(PDF) 48 Page - Applied Micro Circuits Corporation

部件名 PPC405GPR-3JB400Z
功能描述  Power PC 405GPr Embedded Processor
PDF  57 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

PPC405GPR-3JB400Z 数据表(HTML) 48 Page - Applied Micro Circuits Corporation

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405GPr – Power PC 405GPr Embedded Processor
48
AMCC
Revision 2.04 – September 7, 2007
Data Sheet
Internal Peripheral Interface
IICSCL
na
na
na
na
15.3
10.2
IICSDA
na
na
na
na
15.3
10.2
UART0_CTS
na
na
10.3
7.1
UART0_DCD
na
na
10.3
7.1
UART0_DSR
na
na
10.3
7.1
UART0_DTR
10.3
7.1
UART0_RI
na
na
10.3
7.1
UART0_RTS
na
na
10.3
7.1
UART0_Rx
na
na
10.3
7.1
UART0_Tx
na
na
10.3
7.1
UART1_RTS/
UART1_DTR
na
na
10.3
7.1
UART1_DSR/
UART1_CTS
na
na
na
na
UART1_Rx
na
na
na
na
UART1_Tx
na
na
10.3
7.1
UARTSerClk
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
10.3
7.1
JTAG Interface
TCK
na
na
async
TDI
na
na
async
TDO
10.3
7.1
async
TMS
na
na
async
TRST
na
na
async
System Interface
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO24
10.3
7.1
Halt
dc
dc
na
na
na
na
async
SysClk
na
na
na
na
SysErr
na
na
10.3
7.1
async
SysReset
10
1
10.3
7.1
async
TestEn
dc
dc
na
na
na
na
async
TmrClk
dc
dc
na
na
na
na
async
I/O Specifications—Group 1 (Sheet 2 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)



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