4

 2004 Semtech Corp.

www.semtech.com

SC2672

POWER MANAGEMENT

Pin Configuration

Ordering Information

EXPANDED PIN DESCRIPTION

Pin 1: (AGND)

Analog GND.

Return of analog signals and bias of chip

Pin 3: (VCC)

Bias for chip 3V to 15V.

Pin 2, 15: (FB2, FB1)

“-” inputs of error amplifiers.

Pin 4, 13: (SC2, SC1)

Output UVLO programmation.

Pin 5, 12: (BST2, BST1)

BST signal. Supply for high side driver.

Can be connected to a high enough voltage source.

Usually connected to bootstrap circuit.

Pin 6, 11: (DH2, DH1)

DH signal (Drive High).

Gate drive for top MOSFETs.

Requires a small serie resistor.

Pin 7, 10: (DL2, DL1)

DL signal (Drive Low).

Gate drive for bottom MOSFETs.

Requires a small serie resistor.

Pin 8: (PGND)

Power GND. Return of gate drive currents.

Pin 9: (BSTC)

Supply for bottom MOSFETs gate drive.

Pin 14: (SS/ENA)

Soft start pin. Internal current source connected to

external capacitor.

Inhibits he chip if pulled down.

Pin 16: (PGOOD)

Power good signal.

Open collector signal .

Turns to 0 if output voltage is outside the power good

window.

e

c

i

v

e

D

)

1

(

e

g

a

k

c

a

P

R

T

S

2

7

6

2

C

S

6

1

-

C

I

O

S

T

R

T

S

2

7

6

2

C

S

)

2

(

Notes:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

(2) Lead free product.

Pin Descriptions

1

2

3

4

5

6

7

8

PGOOD

AGND

TOP VIEW

(16 Pin SOIC)

13

12

14

15

16

11

10

9

FB1

FB2

SS/ENA

VCC

SC1

SC2

BST1

BST2

DH1

DH2

DL1

DL2

BSTC

PGND