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SC2672

POWER MANAGEMENT

Power and signal traces must be kept separated for noise

considerations. Feedback, current sense traces and ana-

log ground should not cross any traces or planes carrying

high switching currents, such as the input loop or the

phase node.

The input loop, consisting of the input capacitors and

both MOSFETs must be kept as small as possible. All of

the high switching currents occur in this loop. The en-

closed loop area must be kept small to minimize induc-

tance and radiated and conducted emissions. Designing

for minimum trace length is not always the best approach,

often a more optimum layout can be achieved by keep-

ing loop area constraints in mind.

It is important to keep gate lengths short, the IC must be

close to the power switches. This is more difficult in a

dual channel device than a single and requires that the

two power paths run on either side of a centrally located

controller.

Grounding requirements are always conflicting in a buck

converter, especially at high power, and the trick is to

achieve the best compromise. Power ground (PGND)

should be returned to the bottom MOSFET source to pro-

vide the best gate current return path. Analog ground

(GND) should be returned to the ground side of the out-

put capacitors so that the analog circuitry in the control-

ler has an electrically quiet reference and to provide the

greatest feedback accuracy. The problem is that the dif-

ferential voltage capability of the two IC grounds is lim-

ited to about 1V for proper operation and so the physical

separation between the two grounds must also be mini-

mized. If the grounds are too far apart, fast current tran-

sitions in the connection can generate voltage spikes

exceeding the 1V capability, resulting in unstable and er-

ratic behavior.

The feedback divider must be close to the IC and be

returned to analog ground. Current sense traces must

be run parallel and close to each other and to analog

ground.

The IC must have a ceramic decoupling capacitor across

its supply pins, mounted as close to the device as pos-

sible. The small ceramic, noise-filtering capacitors on the

current sense lines should also be placed as close to the

IC as possible.

Layout Guidelines