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SC2672 数据表(PDF) 7 Page - Semtech Corporation

部件名 SC2672
功能描述  Dual Synchronous Voltage Mode Controller
PDF  9 Pages
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制造商  SEMTECH [Semtech Corporation]
网页  http://www.semtech.com
标志 SEMTECH - Semtech Corporation

SC2672 数据表(HTML) 7 Page - Semtech Corporation

  SC2672 Datasheet HTML 1Page - Semtech Corporation SC2672 Datasheet HTML 2Page - Semtech Corporation SC2672 Datasheet HTML 3Page - Semtech Corporation SC2672 Datasheet HTML 4Page - Semtech Corporation SC2672 Datasheet HTML 5Page - Semtech Corporation SC2672 Datasheet HTML 6Page - Semtech Corporation SC2672 Datasheet HTML 7Page - Semtech Corporation SC2672 Datasheet HTML 8Page - Semtech Corporation SC2672 Datasheet HTML 9Page - Semtech Corporation  
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 2004 Semtech Corp.
www.semtech.com
SC2672
POWER MANAGEMENT
Main Loop(s)
The SC2672 is a dual, voltage mode synchronous Buck
controller, the two separate channels are identical and
share only IC supply pins (Vcc and GND), output driver
ground (PGND) and pre-driver supply voltage (BSTC).
They also share a common oscillator generating a
sawtooth waveform for channel 1 and an dephased
sawtooth for channel 2. Channel 2 has both inputs of
the error amplifier uncommitted and available externally.
a) Two independent channels with either common
or different input voltages and different output volt-
ages. The two channels each have their own volt-
age feedback path from their own output. In this
mode, positive inputs of error amplifier 2 are con-
nected externally to Vref. If the application uses a
common input voltage, the sawtooth phase shift
between the channels provides some measure of
input ripple current cancellation.
Applications Information - Theory of Operation
Power Good
The controller provides a power good signal. This is an
open collector output, which is pulled low if the output
voltage is outside of the power good window.
Soft Start/Enable
The Soft Start/Enable (SS/ENA) pin serves several func-
tions. If held below the Soft Start Enable threshold, both
channels are inhibited. DH1 and DH2 will be low, turning
off the top FETs. Between the Soft Start Enable thresh-
old and the Soft Start End threshold, the duty cycle is
allowed to increase. At the Soft Start End threshold,
maximum duty cycle is reached. In practical applications
the error amplifier will be controlling the duty cycle be-
fore the Soft Start End threshold is reached. To avoid
boost problems during startup in current share mode,
both channels start up in asynchronous mode, and the
bottom FET body diode is used for recirculating current
during the FET off time. When the SS/ENA pin reaches
the Soft Start Transition threshold, the channels begin
operating in synchronous mode for improved efficiency.
The soft start pin sources approximately 25uA and soft
start timing can be set by selection of an appropriate
soft start capacitor value.



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