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 2006 Semtech Corp.

www.semtech.com

SC4601

POWER MANAGEMENT

Applications Information - (Cont.)

Layout Guideline

In order to achieve optimal electrical, thermal and noise

performance for high frequency converters, special at-

tention must be paid to the PCB layouts. The goal of lay-

out optimization is to identify the high di/dt loops and

minimize them. The following guideline should be used to

ensure proper functions of the converters.

1. A ground plane is recommended to minimize noises

and copper losses, and maximize heat dissipation.

2. Start the PCB layout by placing the power compo-

nents first. Arrange the power circuit to achieve a

clean power flow route. Put all the connections on

one side of the PCB with wide copper filled areas if

possible.

3. The Vcc bypass capacitor should be placed next to

the Vcc and GND pins.

4. The trace connecting the feedback resistors to the

output should be short, direct and far away from the

noise sources such as switching node and switching

components.

5. Minimize the traces between PDRV/NDRV and the

gates of the MOSFETs to reduce their impedance to

drive the MOSFETs.

6. Minimize the loop including input capacitors, top/bot-

tom MOSFETs. This loop passes high di/dt current.

Make sure the trace width is wide enough to reduce

copper losses in this loop.

7. ISET and PHASE connections to P-MOSFET for cur-

rent sensing must use Kelvin connections.

8. Maximize the trace width of the loop connecting the

inductor, bottom MOSFET and the output capacitors.

9. Connect the ground of the feedback divider and the

compensation components directly to the GND pin

of the SC4601 by using a separate ground trace.

Then connect this pin to the ground of the output

capacitor as close as possible.