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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITE2 数据表(PDF) 101 Page - STMicroelectronics |
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ST7LITE2 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 133 page  ST7LITE2 101/133 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to fin- ish the current instruction execution. 13.5.2 Auto Wakeup from Halt Oscillator (AWU) Note: 1. Guaranteed by Design. Symbol Parameter 1) Conditions Min Typ 2) Max Unit tc(INST) Instruction cycle time fCPU=8MHz 23 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time 3) tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 10 22 tCPU 1.25 2.75 µs Symbol Parameter 1) Conditions Min Typ Max Unit fAWU AWU Oscillator Frequency 50 125 250 kHz tRCSRT AWU Oscillator startup time 50 µs 1 |
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