ST7LITE2_06 datasheet(46/133 Pages) STMICROELECTRONICS

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ST7LITE2

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10 I/O PORTS

10.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port can

contain up to 8 pins. Each pin can be programmed

independently either as a digital input or digital

output. In addition, specific pins may have several

other functions. These functions can include exter-

nal interrupt, alternate signal input/output for on-

chip peripherals or analog input.

10.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Regis-

ter (DDR) are always associated with each port.

The Option Register (OR), which allows input/out-

put options, may or may not be implemented. The

following description takes into account the OR

device specific information.

An I/O pin is programmed using the corresponding

bits in the DDR, DR and OR registers: bit x corre-

sponding to pin x of the port.

Figure 31 shows the generic I/O block diagram.

10.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this

mode, reading its DR bit returns the digital value

from that I/O pin.

If an OR bit is available, different input modes can

be configured by software: floating or pull-up. Re-

fer to I/O Port Implementation section for configu-

ration.

Notes:

1. Writing to the DR modifies the latch value but

does not change the state of the input pin.

2. Do not use read/modify/write instructions

(BSET/BRES) to modify the DR register.

10.2.1.1 External Interrupt Function

Depending on the device, setting the ORx bit while

in input mode can configure an I/O as an input with

interrupt. In this configuration, a signal edge or lev-

el input on the I/O generates an interrupt request

via the corresponding interrupt vector (eix).

Falling or rising edge sensitivity is programmed in-

dependently for each interrupt vector. The Exter-

nal Interrupt Control Register (EICR) or the Miscel-

laneous Register controls this sensitivity, depend-

ing on the device.

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

in section 2 on page 6 and interrupt section).

If several I/O interrupt pins on the same interrupt

vector are selected simultaneously, they are logi-

cally combined. For this reason if one of the inter-

rupt pins is tied low, it may mask the others.

External interrupts are hardware interrupts. Fetch-

ing the corresponding interrupt vector automatical-

ly clears the request latch. Changing the sensitivity

of a particular external interrupt clears this pending

interrupt. This can be used to clear unwanted

pending interrupts.

Spurious interrupts

When enabling/disabling an external interrupt by

setting/resetting the related OR register bit, a spu-

rious interrupt is generated if the pin level is low

and its edge sensitivity includes falling/rising edge.

This is due to the edge detector input which is

switched to '1' when the external interrupt is disa-

bled by the OR register.

To avoid this unwanted interrupt, a "safe" edge

sensitivity (rising edge for enabling and falling

edge for disabling) has to be selected before

changing the OR register bit and configuring the

appropriate sensitivity again.

Caution: In case a pin level change occurs during

these operations (asynchronous signal input), as

interrupts are generated according to the current

sensitivity, it is advised to disable all interrupts be-

fore and to reenable them after the complete pre-

vious sequence in order to avoid an external inter-

rupt occurring on the unwanted edge.

This corresponds to the following steps:

1. To enable an external interrupt:

– set the interrupt mask with the SIM instruction

(in cases where a pin level change could oc-

cur)

– select rising edge

– enable the external interrupt through the OR

– select the desired sensitivity if different from

rising edge

– reset the interrupt mask with the RIM instruc-

tion (in cases where a pin level change could

occur)

2. To disable an external interrupt:

– set the interrupt mask with the SIM instruction

SIM (in cases where a pin level change could

occur)

– select falling edge

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