ST7LITE2_06 datasheet(44/133 Pages) STMICROELECTRONICS

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ST7LITE2

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POWER SAVING MODES (Cont’d)

Figure 30. AWUFH Mode Flow-chart

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only an AWUFH interrupt and some specific in-

terrupts can exit the MCU from HALT mode (such

as external interrupt). Refer to Table 5, “Interrupt

Mapping,” on page 35 for more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

5. If the PLL is enabled by option byte, it outputs

the clock after an additional delay of tSTARTUP (see

Figure 12).

RESET

INTERRUPT 3)

CPU

MAIN OSC

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

MAIN OSC

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY5)

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

CYCLE

AWU RC OSC

OFF

AWU RC OSC

OFF

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

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