SC412AEVB datasheet(13/22 Pages) SEMTECH

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SC412A

POWER MANAGEMENT

Layout Guidelines

These requirements (650μF, 10.8mΩ) can be met using

two capacitors, 330μF 20mΩ.

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 0.75V reference, the DL output

is high and the low-side mosfet is on. During this time, the

voltage across the inductor is approximately - VOUT. This

causes a downslope or falling di/dt in the inductor. If the

load di/dt is not much faster than the di/dt in the inductor,

then the inductor current can track change in load current,

and there will be relatively less overshoot from a load

release. The following can used to calculate the needed

capacitance for a given dILOAD/dt:

Peak inductor current,

ILPEAK = I

LOADMAX + 1/2 • IRIPPLEMAX

ILPEAK = 10 + 1/2 • 4.05 = 12.02A

Rate of change of Load current = dILOAD/dt

IMAX = maximum load release = 10A

COUT = ILPEAK • (L •ILPEAK / VOUT - IMAX/dILOAD/dt)

2 • (VPEAK - VOUT)

Example: Load dI/dt = 2.5A/usec

This would cause the output current to move from 10A to

zero in 4μsec.

COUT = 12.45•(0.7μH•12.45/1.15 - 10/(2.5/1μsec)

2 •(1.23 - 1.15)

COUT = 278 μF

Stability Considerations

Unstable operation shows up in two related but distinctly

different ways: double-pulsing and fast-feedback loop

instability. double-pulsing occurs due to switching noise

seen at the FB input or because the ESR is too low, caus-

ing insufﬁcient voltage ramp in the FB signal. This causes

the error ampliﬁer to trigger prematurely after the 350ns

minimum off-time has expired. double-pulsing will result

in higher ripple voltage at the output, but in most cases

is harmless. In some cases, however, double-pulsing can

indicate the presence of loop instability, which is caused

by insufﬁcient ESR.

One simple way to solve this problem is to add some trace

resistance in the high current output path. A side effect of

doing this is output voltage droop with load. Another way

to eliminate doubling-pulsing is to add a small (e.g. 10pF)

capacitor across the upper feedback resistor divider net-

work, (this capacitor is shown in Figure 6). This capacitance

should be left out until conﬁrmation that double-pulsing

exists. Adding this capacitance will add a zero in the trans-

fer function and should eliminate the problem. It is best to

leave a spot on the PCB in case it is needed.

To FB pin

VOUT

Figure 6.

Loop instability can cause oscillations at the output as a

response to line or load transients. These oscillations can

trip the over-voltage protection latch or cause the output

voltage to fall below the tolerance limit.

The best way for checking stability is to apply a zero-to-

full load transient and observe the output voltage ripple

envelope for overshoot and ringing. Over one cycle of ring-

ing after the initial step is a sign that the ESR should be

increased.

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