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SC4624SETRT 数据表(PDF) 15 Page - Semtech Corporation

部件名 SC4624SETRT
功能描述  Low Input Voltage, High Efficiency, 4A Integrated FET Synchronous Step down DC/DC Regulator
PDF  20 Pages
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制造商  SEMTECH [Semtech Corporation]
网页  http://www.semtech.com
标志 SEMTECH - Semtech Corporation

SC4624SETRT 数据表(HTML) 15 Page - Semtech Corporation

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 2007 Semtech Corp.
www.semtech.com
SC4624
POWER MANAGEMENT
Operation
Application Information (Cont.)
Application Information (Cont.)
where
)
C
C
(
R
1
2
1
7
I
+
⋅
=
ω
2
1
1
Z
C
R
1
⋅
=
ω
8
8
7
2
Z
C
)
R
R
(
1
⋅
+
=
ω
2
1
1
2
1
1
P
C
C
R
C
C
⋅
⋅
+
=
ω
9
8
2
P
C
R
1
⋅
=
ω
After the compensation, the converter will have the
following loop gain:
=
where
G
PWM = PWM gain.
V
M = 1.0V, ramp peak to valley voltage of SC4624.
The design guidelines for the SC4624 applications are as
follows:
Set the loop gain crossover corner frequency w
C for
given switching corner frequency w
S = 2pfs,
Place an integrator at the origin to increase DC and
low frequency gains.
Select w
Z1 and wZ2 such that they are placed near wO
to damp the peaking and the loop gain has a -20dB/
dec rate to go across the 0dB line for obtaining a wide
bandwidth.
Cancel the zero from C4’s ESR by a compensator pole
w
P1 (wP1 = wESR = 1/(RCC4)).
Place a high frequency compensator pole w
P2 (wP2 =
pfs) to get the maximum attenuation of the switch-
ing ripple and high frequency noise with the adequate
phase lag at w
C.
The compensated loop gain will be as given as show in
Figure 18.
Figure 18. Asymptotic Diagrams
of Power Stage and Loop Gain
1.
2.
3.
4.
5.
C
L
s
R
L
s
1
C
R
1
s
1
s
1
s
1
s
1
s
1
s
V
V
1
)
s
(
G
)
s
(
G
G
)
s
(
T
1
2
1
4
C
2
P
2
Z
1
P
1
Z
I
I
M
VD
COMP
PWM
+
+
⋅
+
⋅
w
+
⋅
w
+
⋅
w
+
w
+
⋅
⋅
w
⋅
=
⋅
⋅
=
8
C
L
s
R
L
s
1
C
R
1
s
1
s
1
s
1
s
1
s
1
s
V
V
1
)
s
(
G
)
s
(
G
G
)
s
(
T
1
2
1
4
C
2
P
2
Z
1
P
1
Z
I
I
M
VD
COMP
PWM
+
+
⋅
+
⋅
w
+
⋅
w
+
⋅
w
+
w
+
⋅
⋅
w
⋅
=
⋅
⋅
=



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