Architecture features

STi5107

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Architecture features

2.1

Introduction

The STi5107 is a low-cost Omega2 MPEG device that delivers high performance and

integrates features that provide an overall system cost reduction. The device implements a

fully unified DDR/SDR SDRAM based memory architecture that integrates the Omega2

video decoder cell, together with a blitter engine and a multichannel DMA controller to

provide enhanced performance for graphics and real-time stream transfers.

Transfer of data such as pixmaps, audio streams, stills and PES can be performed efficiently

using the STi5107 DMA.

A true-color mode provides OSD graphics allowing the display of RGB16 formats: RGB565,

ARGB1555 and ARGB4444. This directly supports up to 65,536 colors in a region. Alpha

blending by region or by pixel is available for mixing with video and background layers.

The above feature set, guaranties smooth user interface and high performance for

demanding middleware such as MHP™.

2.2

Omega2 (STBus) interconnect

The Omega2 multipath unified interconnect provides high on-chip bandwidth and low

latency accesses between modules. The interconnect operates hierarchically, with latency-

critical modules placed at the top level. The multipath router allows simultaneous access

paths between modules, and simultaneous read and write phases from different

transactions to and from the modules.

2.3

Processor core

The ST20-C106 processor core comprises the well established ST20C1+ CPU running at

200 MHz. It provides a diagnostic controller unit (for low intrusion, real-time debugging), a

memory (4-Kbyte instruction cache, 4-Kbyte data cache and 2-Kbyte SRAM) and a 16 input

priority-level interrupt controller. ST20 has been recognized as the best in class for real time,

mutitasking and low memory footprint CPU. Thanks to ST’s royalty free operating system

(0S20) and the full toolset suite, it makes the perfect development environment for STB

application.

2.4

Memory subsystem

The STi5107 has a local memory interface (LMI) and a peripheral/flash memory interface

(FMI).

The STi5107's LMI is used for all data requirements in unified memory applications,

including graphics, video and audio buffers. It provides 16-bit wide SDR/DDR SDRAM

interface that can operate at 166 MHz for both SDR or DDR memories.

The FMI provides support for 16-bit wide peripherals, flash and synchronous flash.

Instructions can execute in place from flash/SFlash™ on the FMI or can be copied to

SDRAM on the LMI. The following sections overview the different memory interfaces.