STi5107

Architecture features

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2.4.1

Local memory interface

The LMI is a 16-bit wide SDR/DDR SDRAM interface with a peak bandwidth of 532 Mbyte/s

(DDR running @166 MHz). It supports 64-MBit, 128-Mbit, 256-Mbit, or 512-Mbit SDRAM.

The LMI provides a fully cacheable address space for data and instructions, with data

cacheability controlled in 512 Kbyte blocks for up to 8 Mbytes.

2.4.2

Flash memory interface

The FMI provides a glueless interface to SRAM, flash, SFlash and peripherals, in up to four

configurable banks over a 16-bit wide interface. Bus cycle strobe timings can be

programmed from 0 to 15 phases for slower peripherals.

Support is provided for control of DVB-CI and ATAPI connection.

2.5

Transport stream processing

The STi5107 supports single transport stream input.

It is possible to support DVB-CI configurations as shown in Figure 4 and Figure 5.

Figure 4.

Dual DVB-CI support

Figure 5.

Single DVB-CI support

TSIN

STV0288

STi5107

DVB-CI

A

DVB-CI

B

A

B

Buffer commands

TSIN

DVB-CI

STi5107

STV0288

buffer command

A