TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

11

POST OFFICE BOX 655303

timing diagrams

The timing diagrams can be categorized into two major groups: nonconversion and conversion. The

nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion

cycles are those four modes of conversion.

read cycle (read FIFO or read CFR)

read CFR cycle:

The read command is decoded in the first 4 clocks. SDO outputs the contents of the CFR after the 4th SCLK.

SCLK

CS

FS

SDI

INT

EOC

SDO

ID14

ID13

ID12

ID15

OD11 OD10

OD9

OD4

OD3

OD2

OD1

OD0

12

3

4

5

6

713

14

15

16

1

12

ID15

Figure 2. TLV2544/TLV2548 Read CFR Cycle (FS active)

SCLK

CS

FS

SDI

INT

EOC

SDO

ID15

ID14

ID13

ID12

ID14

OD4

OD3

OD2

OD1

OD0

12

3

4

5

6

713

14

15

16

1

12

OD11 OD10

OD9

ID15

Figure 3. TLV2544/TLV2548 Read CFR Cycle (FS = 1)