TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

21

POST OFFICE BOX 655303

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

3

3.3

5.5

V

Analog input voltage (see Note 3)

0

VCC

V

High level control input voltage, VIH

2.1

V

Low-level control input voltage, VIL

0.6

V

Setup time, tsu(CS-SCLK) CS falling edge before

SCLK rising edge (FS=1) or before SCLK falling

VCC = 4.5 V, SCLK = 20 MHz

20

ns

SCLK rising edge (FS=1) or before SCLK falling

edge (when FS is active)

VCC = 3 V, SCLK = 20 MHz

30

ns

Hold time, CS rising edge after SCLK rising edge

(FS=1) or after SCLK falling edge (when FS is

VCC = 4.5 V

10

ns

(FS=1) or after SCLK falling edge (when FS is

active), th(SCLK-CS)

VCC = 3 V

15

ns

Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH)

0.5

SCLKs

Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active),

td(SCLK16L-CSH)

0.5

SCLKs

Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL)

20

ns

Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKL)

30

37

ns

Pulse width, CS high time, twH(CS)

100

ns

Pulse width, FS high time, twH(FS)

0.75

1

SCLKs

SCLK cycle time, VCC = 3 V to 3.6V, tc(SCLK)

67

10000

ns

SCLK cycle time, VCC = 4.5 V to 5.5V, tc(SCLK)

50

10000

ns

Pulse width SCLK low time t L(SCLK)

VCC = 4.5 V

22

ns

Pulse width, SCLK low time, twL(SCLK)

VCC = 3 V

27

ns

Pulse width SCLK high time t H(SCLK)

VCC = 4.5 V

22

ns

Pulse width, SCLK high time, twH(SCLK)

VCC = 3 V

27

ns

Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of

SCLK (FS=1), tsu(DI-SCLK)

25

ns

Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge

of SCLK (FS=1), th(DI-SCLK)

5

ns

Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)

25

ns

Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV)

25

ns

VCC =5 5V

SDO = 0 pF

0.5 SCLK

+ 5

Delay time, delay from SCLK falling edge (FS is

active) or SCLK rising edge (FS=1) to SDO valid

VCC = 5.5 V

SDO = 60 pF

0.5 SCLK

+ 24

ns

active) or SCLK rising edge (FS=1) to SDO valid,

td(SCLK-DOV)

VCC =3 3V

SDO = 0 pF

0.5 SCLK

+ 12

ns

VCC = 3.3 V

SDO = 60 pF

0.5 SCLK

+ 33

Delay time, delay from CS rising edge to SDO 3-state, td(CSH-DOZ)

80

ns

Delay time, delay from 17th SCLK rising edge (FS is active) or the 16th falling edge

(FS=1) to EOC falling edge, td(SCLK-EOCL)

45

ns

Delay time, delay from 16th SCLK falling edge to INT falling edge (FS =1) or from the

17th rising edge SCLK to INT falling edge (when FS active), td(SCLK-INT)

Min t(conv)

µs

Delay time, delay from CS falling edge to INT rising edge, td(CSL-INTH)

50

ns

Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)

100

ns

Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)

50

ns

Pulse width, CSTART low time, twL(CSTART)

Min t(sample)

µs

NOTE 3: When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while

input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to

1 V. (VREFP – VREFM – 1); however, the electrical specifications are no longer applicable.