TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

12

POST OFFICE BOX 655303

read cycle (read FIFO or read CFR) (continued)

FIFO read cycle

The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read

command. The first FIFO content is output immediately before the command is decoded. If this command is

not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read

command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is

because the read cycle does not generate EOC or INT, nor does it carry out any conversion.

SCLK

CS

FS

SDI

INT

EOC

SDO

ID15

ID14

ID13

ID12

OD7

OD5

OD0

12

3

4

5

6

713

14

15

16

12

OD11 OD10

OD9

OD6

OD8

ID15

12

OD10

OD11

ID14

These Devices can Perform Continuous FIFO Read Cycle (FS = 1) Controlled by SCLK, SCLK can Stop Between Each 16 SCLKs.

Figure 4. TLV2544/TLV2548 FIFO Read Cycle (FS = 1)