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P912XDP512F0MPVR 数据表(PDF) 179 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 179 Page - Freescale Semiconductor, Inc |
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179 / 1350 page ![]() Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 179 5.3.2.13 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the result registers based on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 5.3.2.13.1 Left Justified Result Data 5.3.2.13.2 Right Justified Result Data 76543210 R R BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 10-bit data 8-bit data W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH) 76543210 R R BIT 1 U BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) 76543210 R R 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 10-bit data 8-bit data W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH) 76543210 R R BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 10-bit data 8-bit data W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) |
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