P912XDP512F0MPVR datasheet(182/1350 Pages) FREESCALE

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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3)

MC9S12XDP512 Data Sheet, Rev. 2.17

182

Freescale Semiconductor

5.4.2.2

General Purpose Digital Input Port Operation

The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are

multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external

input data that can be accessed through the digital port register PORTAD (input-only).

The analog/digital multiplex operation is performed in the input pads. The input pad is always connected

to the analog inputs of the ATD. The input pad signal is buffered to the digital port registers. This buffer

can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw

excess current when analog potentials are presented at its input.

5.4.2.3

Low Power Modes

The ATD can be conﬁgured for lower MCU power consumption in 3 different ways:

1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due

to the recovery time the result of this conversion should be ignored.

2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D

conversion, but due to the recovery time the result of this conversion should be ignored.

3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D

conversion in progress.

Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the

power down state.

5.5

Resets

At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register

Description section (see Section 5.3, “Memory Map and Register Deﬁnition”), which details the registers

and their bit-ﬁeld.

5.6

Interrupts

The interrupt requested by the ATD is listed in Table 5-24. Refer to the device overview chapter for related

vector address and priority.

See register descriptions for further details.

Table 5-24. ATD Interrupt Vectors

Interrupt Source

CCR

Mask

Local Enable

Sequence complete

interrupt

I bit

ASCIE in ATDCTL2

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